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AS5SP128K32 fiches techniques PDF

Micross Components - Synchronous SRAM

Numéro de référence AS5SP128K32
Description Synchronous SRAM
Fabricant Micross Components 
Logo Micross Components 





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AS5SP128K32 fiche technique
SSRAM
AS5SP128K32
Plastic Encapsulated Microcircuit
4.0Mb, 128K x 32, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
TQFP in copper lead frame for superior thermal
performance
RoHs compliant options available
NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 NC
FAST ACCESS TIMES
Parameter
CycleTime
ClockAccessTime
OutputEnableAccessTime
Symbol 200Mhz 166Mhz 133Mhz 100Mhz Units
tCYC 5.0 6.0 7.5 10.0 ns
tCD 3.0 3.5 4.0 5.0 ns
tOE 3.0 3.5 4.0 5.0 ns
GENERAL DESCRIPTION
The AS5SP128K32 is a 4.0Mb High Performance Synchronous
BLOCK DIAGRAM
OE\
ZZ
CLK
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 32. It integrates
address and control registers, a two (2) bit burst address counter
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
I/O Gating and Control
Memory Array
x36
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
The AS5SP128K32 includes advanced control options including
Global Write, Byte Write as well as an Asynchronous Output
enable. Burst Cycle controls are handled by three (3) input pins,
ADV, ADSP\ and ADSC\. Burst operation can be initiated with
either the Address Status Processor (ADSP\) or Address Status
Cache controller (ADSC\) inputs. Subsequent
DQx, DQPxburst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
A0-Ax
Column
Decode
AS5SP128K32
Rev. 1.4 09/11
Micross Components reserves the right to change products or specications without notice.
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