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PDF AS5SP256K36 Data sheet ( Hoja de datos )
| Número de pieza | AS5SP256K36 | |
| Descripción | Synchronous SRAM | |
| Fabricantes | Micross Components | |
| Logotipo |  |
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COTS PEM
SSRAM
AS5SP256K36
Plastic Encapsulated Microcircuit
9.0Mb, 256K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 DQP
79 DQb
78 DQb
77 VDD
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDD
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDD
53 DQa
52 DQa
51 DQP
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package,
• Available in Industrial, Enhanced, and Mil-Temperature FAST ACCESS TIMES
Operating Ranges
• TQFP in copper lead frame* for superior thermal
performance
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
• RoHs compliant options available
*Consult factory for copper lead frame products
GENERAL DESCRIPTION
The AS5SP256K36 is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
Performance CMOS technology and is organized as a
256K x 36. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed
and synchronous to the rising edge of clock.
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
The AS5SP256K36 includes advanced control options
including Global Write, Byte Write as well as an
Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either the
DQx, DQP Address Strobe Processor (ADSP\) or Address Strobe
controller (ADSC\) inputs. Subsequent burst addresses
are generated internally in the system’s burst sequence
control block and are controlled by Address Advance
(ADV\) control input.
AS5SP256K36
Rev. 2.1 09/11
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
SYNCHRONOUS TRUTH TABLES
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
Notes:
CE2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
CE3\
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
ADSP\
X
L
L
H
H
L
H
H
H
X
H
X
H
X
H
X
ADSC\
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV\
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
WT / RD
X
X
X
X
X
X
WT
RD
RD
RD
WT
WT
RD
RD
WT
WT
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
CLK
Address Accessed
NA
NA
NA
NA
NA
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
COTS PEM
SSRAM
AS5SP256K36
Operation
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
Suspend Burst, WRITE
BURST SEQUENCE TABLES
CAPACITANCE
Burst Control
Pin [MODE]
First Address
State
HIGH
Fourth Address
Case 1
A1 A0
0
0
1
1
Interleaved Burst
Case 2
A1 A0
00
10
01
11
1
0
1
0
Burst Control
Pin [MODE]
First Address
State
LOW
Fourth Address
Case 1
A1 A0
0
0
1
1
Linear Burst
Case 2
A1 A0
00
11
01
10
1
0
1
0
WRITE TABLE
GW\
H
H
H
H
H
H
L
BW\ BWa\ BWb\ BWc\ BWd\
HXXXX
L HHHH
L LHHH
L H L HH
LHHL L
LLLLL
XXXXX
Case 3
A1 A0
1
1
0
0
0
1
0
1
Case 3
A1 A0
1
1
0
0
0
1
0
1
Case 4
Parameter
A1 A Input Capacitance
1 Input/Output Capacitance
1
0
Clock Input Capacitance
0
Symbol
CI
CIO
CCLK
Max.
6
8
6
Units
pF
pF
pF
ASYNCHRONOUS TRUTH TABLE
Case 4
A1 A Operation
ZZ OE\
1
0
0
Power-Down (SLEEP)
READ
H
L
X
L
1 LH
I/O Status
High-Z
DQ
High-Z
WRITE
LX
Din, High-Z
De-Selected
LX
High-Z
Operation
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
AC TEST LOADS
Output
Zo=50 ohm
Rt = 50 ohm
ABSOLUTE MAXIMUM RATINGS
Diagram [A] 30 pF
Absolute Maximum Ratings
Parameter
Symbol Min.
Max.
Voltage on VDD Pin
Voltage on VDDQ Pins
Voltage on Input Pins
Voltage on I/O Pins
Power Dissipation
Storage Temperature
Operating Temperatures
[Screening Levels]
VDD
VDDQ
VIN
VIO
PD
tSTG
/IT
/ET
-0.3
VDD
-0.3
-0.3
-65
-40
-40
4.6
VDD+0.3
VDDQ+0.3
1.6
150
85
105
/XT -55 125
Units
V
V
V
V
W
RC
RC
RC
RC
Vt= Termination Voltage
Rt= Termination Resistor
3.3/2.5v
R= 351 [email protected]
R= 1538 [email protected]
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
R= 317 [email protected]
R= 1667 [email protected]
Output
5 pF
Diagram [B]
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum conditions
for any duration or segment of time may affect device reliability.
AS5SP256K36
Rev. 2.1 09/11
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
COTS PEM
SSRAM
AS5SP256K36
Power Down (SNOOZE MODE)
Power Down or Snooze is a Power conservation mode which when building large/very dense arrays, using multiple devices
in a multi-banked or paged array, can greatly reduce the Operating current requirements of your total memory array solution.
The device is placed in this mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the
array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SNOOZE) mode is done
so by de-asserting the ZZ pin .
While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the
mode are not considered valid nor is the completion of the operation guaranteed. The device must be de-selected prior to
entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the duration of ZZ recovery
time (tZZREC).
ZZ MODE ELECTRICAL CHARACTERISTICS
Parameter
Power Down (SNOOZE) Mode
ZZ Active (Signal HIGH) to Power Down
ZZ Inactive (Signal Low) to Power Up
Symbol
IDDzz
tZZS
tZZR
Test Conditon
ZZ >/- VDD - 0.2V
ZZ >/- VDD - 0.2V
ZZ </- 0.2V
ZZ MODE TIMING DIAGRAM
Min.
2 tCYC
Max.
75
2 tCYC
Units
mA
ns
ns
CLK
ADSP\
ADSC\
CEx\
CE2
ZZ
IDD
tZZS
tZZREC
IDDzz
AS5SP256K36
Rev. 2.1 09/11
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AS5SP256K36.PDF ] | |
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