PDF AS4C4M16S-6TCN Data sheet ( Hoja de datos )

Número de pieza	AS4C4M16S-6TCN
Descripción	64Mb / 4M x 16 bit Synchronous DRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! AS4C4M16S Revision History AS4C4M16S- 54PIN 400 MIL PLASTIC TSOP II PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Removed 6TAN –– automotive temp page 1 and page 52 (see separate datasheet for this option) Added 6TCN – 166MHz clock – commercial temp page 1 and page 52 Added in temperature range to page 1 * Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C) Date February 2011 May 2014 May 2014 May 2014 Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 1 page FEBRUARY 2011 AS4C4M16S LDQM, UDQM Input Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode. DQ0-DQ15 Input / Data I/O: The DQ0-15 input and output data are synchronized with the positive Output edges of CLK. The I/Os are maskable during Reads and Writes. NC/RFU - No Connect: These pins should be left unconnected. VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0V) VDD Supply Power Supply: +3.3V ± 0.3V VSS Supply Ground 4 Rev2.0 May 2014 5 Page FEBRUARY 2011 AS4C4M16S A write burst without the auto precharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). CLK COMMAND T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP DQ DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 Figure 11. Write Interrupted by a Write (Burst Length = 4) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed. CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP CAS# latency=2 tCK2, DQ DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS# latency=3 tCK3, DQ DIN A0 don’t care don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without t he auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data- in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). 10 Rev2.0 May 2014 11 Page

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