PDF AS5LC256K16 Data sheet ( Hoja de datos )

Número de pieza	AS5LC256K16
Descripción	256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
Fabricantes	Micross Components
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No Preview Available ! PRELIMINARY SRAM AS5LC256K16 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES • High-speed access time: 10, 15 & 20ns • Available in Mil-Temp, Enhanced & Industrial Ranges • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby • Single power supply: VDD = 3.3V ± 5% • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes •TSOPII in copper lead frame for superior thermal performance • RoHs compliant options available Consult factory for /XT product. PIN CONFIGURATIONS 44-pin TSOPII A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 A17 43 A16 42 A15 41 OE 40 UB 39 LB 38 I/O15 37 I/O14 36 I/O13 35 I/O12 34 GND 33 VDD 32 I/O11 31 I/O10 30 I/O9 29 I/O8 28 NC 27 A14 26 A13 25 A12 24 A11 23 A10 FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT CE OE WE CONTROL CIRCUIT UB LB 256K x 16 MEMORY ARRAY COLUMN I/O A0ͲA17 I/OoͲI/O15 CE\ OE\ WE\ LB\ UB\ NC VDD GND AddressInputs DataInputs/Outputs ChipEnableInput OutputEnableInput WriteEnableInput LowerͲbyteControl(I/O0ͲI/O7) UpperͲbyteControl(I/O8ͲI/O15) NoConnection Power Ground GENERAL DESCRIPTION The Micross AS5LC256K16 is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabri- cated using Micross’ high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consump- tion devices. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. For more products and information please visit our web site at www.micross.com Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE\ and OE\. The active LOW Write Enable (WE\) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The AS5LC256K16 is packaged in JEDEC standard 44-pin TSOPII in copper lead frame for superior thermal performance. RoHs compliant options are available. AS5LC256K16 Rev. 0.1 09/11 Micross Components reserves the right to change products or speciﬁcations without notice. 1 1 page PRELIMINARY SRAM AS5LC256K16 READ CYCLE SWITCHING CHARACTERISTICS1 (Over Operating Range) Symbol tRC tAA tCHA tACE tDOE tHZOE2 tLZOE2 tHZCE2 tLZCE2 tBA tHZB2 tLZB2 Notes: Parameter ReadCycleTime AddressAccessTime OutputHoldTime CE\AccessTime OE\AccessTime OE\toHighͲZOutput OE\toLowͲZOutput CE\toHighͲZOutput CE\toLowͲZOutput LB\,UB\AccessTime LB\,UB\toHighͲZOutput LB\,UB\toLowͲZOutput Ͳ10 Min Max 10 Ͳ 0 10 2.0 Ͳ Ͳ 10 Ͳ 4.5 Ͳ 4 0 Ͳ 04 2 Ͳ Ͳ 6.5 04 0 Ͳ Ͳ15 Min Max 15 Ͳ Ͳ 15 2.0 Ͳ Ͳ 15 Ͳ 6 Ͳ 6 0 Ͳ 06 2 Ͳ Ͳ 7 06 0 Ͳ Ͳ20 Min Max 20 Ͳ Ͳ 20 2 Ͳ Ͳ 20 Ͳ 8 Ͳ 8 0 Ͳ 08 2 Ͳ Ͳ 8 08 0 Ͳ Unit ns ns ns ns ns ns ns ns ns ns ns ns 1.Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0Vandoutputloading specifiedinFigure1. 2.TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteadyͲstatevoltage. AS5LC256K16 Rev. 0.1 09/11 Micross Components reserves the right to change products or speciﬁcations without notice. 5 5 Page PRELIMINARY SRAM AS5LC256K16 MECHANICAL DEFINITION 44-Pin TSOPII (Package Designator DGC & DGCR) AS5LC256K16 Rev. 0.1 09/11 11 Micross Components reserves the right to change products or speciﬁcations without notice. 11 Page

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Número de pieza	Descripción	Fabricantes
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