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PDF AS8SLC512K32PECA Data sheet ( Hoja de datos )

Número de pieza AS8SLC512K32PECA
Descripción High Speed Static RAM
Fabricantes Micross Components 
Logotipo Micross Components Logotipo



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No Preview Available ! AS8SLC512K32PECA Hoja de datos, Descripción, Manual

iPEM
16 Mb ASYNC SRAM
AS8SLC512K32PECA
16Mb, 512Kx32 CMOS 3.3V, High Speed Static RAM
Integrated Plastic Encapsulated Microcircuit
FEATURES
Integrated Real-Time Memory Array Solution
No latency or refresh fycles
Parallel Read/Write Interface
User Congurable via multiple enables
Random Access Memory Array
Fast Access Times: 12, 15, 20, and 25ns
TTL Compatible I/O
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99 JEDEC M0-47AE
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum Noise Immunity
Single 3.3V (±10%) Supply Operation
DESCRIPTION
The AS8SLC512K32 is a high speed, 3.3V, 16Mb SRAM.
The device is available with access times of 12, 15, 20
and 25ns creating a zero wait state/latency, real-time
memory solution. The high speed, 3.3V supply voltage
and control lines,make the device ideal for all your
real-time computer memory requirements.
The device can be congured as a 512K x 32 and used to
create a single chip external data /program memory array
solution or via use of the individual chip enable lines, be
recongured as a 1M x 16 or 2M x 8.
The device provides a 50+% space savings when
compared to four 512K x 8, 36 pin SOJs. In addition the
AS8SLC512K32 has only a 24pF load on the Addr. lines
vs. ~40pF for four plastic SOJs.
PIN CONFIGURATIONS AND BLOCK DIAGRAM (PECA Package)
DQ17 10
DQ18 11
DQ19 12
Vss 13
DQ20 14
DQ21 15
DQ22 16
DQ23 17
Vcc 18
DQ24 19
DQ25 20
DQ26 21
DQ27 22
Vss 23
DQ28 24
DQ29 25
DQ30 26
60 DQ14
59 DQ13
58 DQ12
57 Vss
56 DQ11
55 DQ10
54 DQ09
53 DQ08
52 Vcc
51 DQ07
50 DQ06
49 DQ05
48 DQ04
47 Vss
46 DQ03
45 DQ02
44 DQ01
PIN NAMES
A0 - A18 Address Inputs
E0\ - E3\ Chip Enables
W\ Write Enables
G\ Output Enable
DQ0 - DQ31 Common Data Input/Output
Vcc Power (+5V ± 10%)
Vss Ground
NC No Connection
BYTE CONTROL TABLE
Chip
Byte
Enable
Control
E0\ DQ0-7
E1\ DQ8-15
E2\ DQ16-23
E3\ DQ24-31
A0-A18
G\
W\
E0\
E1\
E2\
E3\
19
512K x 32
Memory Array
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
AS8SLC512K32PECA
Rev. 0.2 03/11
Micross Components reserves the right to change products or specications without notice.
1

1 page




AS8SLC512K32PECA pdf
iPEM
16 Mb ASYNC SRAM
AS8SLC512K32PECA
WRITE CYCLE 2 - E\ CONTROLLED
tAVAV
A
tAVEL
tELEH
E\
W\
tAVEH
tWLEH
D
Q HIGH Z
tEHAX
tDVEH
tEHDX
DATA VALID
PACKAGE DRAWING
Package No. 99
68 Lead PLCC
JEDEC MO-47AE
0.995
Max
0.956
Max
0.995 0.956
Max Max
0.180
Max
0.040
Max
0.020
0.015
0.930
0.890
0.050
BSC
0.115
Max
AS8SLC512K32PECA
Rev. 0.2 03/11
Micross Components reserves the right to change products or specications without notice.
5

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