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PDF MT48H8M32LFF5-10 Data sheet ( Hoja de datos )
| Número de pieza | MT48H8M32LFF5-10 | |
| Descripción | MOBILE SDRAM | |
| Fabricantes | Micron Technology | |
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256Mb: x32 Mobile SDRAM
Features
Mobile SDRAM
MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/mobile
Features
• Low voltage power supply
• Partial array self refresh power-saving mode
• Temperature Compensated Self Refresh (TCSR)
• Deep power-down mode
• Programmable output drive strength
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto
precharge, and auto refresh modes
• Self-refresh mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Commercial and industrial temperature ranges
• Supports CAS latency of 1, 2, 3
Table 1: Addressing
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
8 Meg x 32
2 Meg x 32 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
Options
• VDD/VDDQ
• 3.3V/3.3V
• 2.5V/2.5V
• 1.8V/1.8V
• Configurations
• 8 Meg x 32 (2 Meg x 32 x 4 banks)
• Package/Ballout
• 90-ball VFBGA (8mm x 13mm)
(Standard)
• 90-ball VFBGA (8mm x 13mm)
(Lead-free)
• Timing (Cycle Time)
• 7.5ns @ CL = 3 (133 MHz)
• 7.5ns @ CL = 2 (104 MHz)
• 8ns @ CL = 3 (125 MHz)
• 8ns @ CL = 2 (104 Mhz)
• 10ns @ CL = 3 (100 MHz)
• 10ns @ CL = 2 (83 Mhz)
• Operating Temperature Range
• Commercial (0° to +70°C)
• Industrial (-40°C to +85°C)
Marking
LC
V
H
8M32
F5
B5
-75
-75
-8
-8
-10
-10
None
IT
Table 2: Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
-75
-8
-10
-75
-8
-10
Clock
Frequency
133 MHz
125 MHz
100 MHz
133 MHz
104 MHz
83 MHz
Access Time
CL = 2
–
–
–
7ns
8ns
8ns
CL = 3
6ns
7ns
7ns
–
–
-
Setup
Time
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
Hold
Time
1ns
1ns
1ns
1ns
1ns
1ns
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_1.fm - Rev. G 6/05
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
256Mb: x32 Mobile SDRAM
FBGA Part Number System
Table 3: Cross Reference For VFBGA Device Marking
Part Number
MT48LC8M32LFF5-75
MT48LC8M32LFF5-8
MT48LC8M32LFF5-10
MT48LC8M32LFB5-75
MT48LC8M32LFB5-8
MT48LC8M32LFB5-10
MT48V8M32LFF5-75
MT48V8M32LFF5-8
MT48V8M32LFF5-10
MT48V8M32LFB5-75
MT48V8M32LFB5-8
MT48V8M32LFB5-10
MT48H8M32LFF5-75
MT48H8M32LFF5-8
MT48H8M32LFF5-10
MT48H8M32LFB5-75
MT48H8M32LFB5-8
MT48H8M32LFB5-10
VDD/VDDQ
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
Architecture
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
VFBGA
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
Production
Marking
D9FMQ
D9CCH
D9CCK
D9FMX
D9CCW
D9CCZ
D9FMS
D9CCM
D9CCP
D9FMZ
D9CDC
D9CDF
D9FMV
D9CCR
D9CCT
D9FNB
D9CDJ
D9CDL
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part mark-
ing that is different from the part number. For a quick conversion of an FBGA code, see
the FBGA part marking decoder on Micron’s Web site, www.micron.com/decoder.
General Description
The Micron® 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32
bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high-
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
256Mb: x32 Mobile SDRAM
Register Definition
Figure 3: Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12 11 10 9 8 7
0 0 Reserved* WB Op Mode
6 543
CAS Latency BT
2 10
Burst Length
Mode Register (Mx)
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M8 M7 M6-M0 Operating Mode
0 0 Defined Standard Operation
--
- All other states reserved
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
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