|
|
PDF MT48H8M16LF Data sheet ( Hoja de datos )
| Número de pieza | MT48H8M16LF | |
| Descripción | Synchronous DRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT48H8M16LF (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Synchronous DRAM
MT48H8M16LF - 2 Meg x 16 x 4 banks
128Mb: x16 – Mobile SDRAM
Features
Features
• Temperature compensated self refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto
precharge, and auto refresh modes
• Self refresh mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial array self refresh power-saving mode
• Deep power-down mode
• Programmable output drive strength
• Operating temperature ranges:
Extended (-25°C to +85°C)
Industrial (-40°C to +85°C)
Options
Marking
• VDD/VDDQ
1.8V/1.8V
H
• Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
• Package/Ball out
54-ball FBGA, 8mm x 8mm (standard)
F4
54-ball FBGA, 8mm x 8mm (lead-free)
B4
• Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
-8
9.6ns @ CL = 3 (104 MHz)
-10
• Operating Temperature
Extended (-25°C to +85°C)
none
Industrial (-40°C to +85°C)
IT
FBGA Part Number System
Due to space limitations, FBGA-packaged components
have an abbreviated part marking that is different from
the part number. For a quick conversion of an FBGA
code, see the FBGA Part Marking Decoder on the
Micron Web site, www.micron.com/decoder.
Figure 1: 54-Ball FBGA Assignment
(Top View)
123456789
A VSS DQ15 VSSQ
VDDQ DQ0
VDD
B DQ14 DQ13 VDDQ
VSSQ
DQ2
DQ1
C DQ12 DQ11 VSSQ
VDDQ DQ4
DQ3
D DQ10 DQ9 VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD LDQM DQ7
F UDQM CLK
CKE
CAS# RAS#
WE#
G NC/A12 A11
A9
BA0 BA1
CS#
H A8 A7 A6
A0 A1 A10
J VSS A5 A4
Top View
(Ball Down)
A3 A2 VDD
Table 1: Address Table
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
8 Meg x 16
2 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
Table 2: Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
-8
-10
-8
-10
Clock
Frequency
125 MHz
104 MHz
104 MHz
83 MHz
Access Time
Setup Hold
CL = 2 CL = 3 Time Time
6ns 2.5ns 1ns
– 7ns 2.5ns 1ns
8ns – 2.5ns 1ns
8ns – 2.5ns 1ns
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_1.fm - Rev. E 3/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
128Mb: x16 Mobile SDRAM
General Description
Figure 2: Part Numbering Diagram
Example Part Number: MT48H8M16LFF4-8 IT
MT48 VDD/ Configuration
VDDQ
–
Package
Speed
Temp
VDD/VDDQ
1.8/1.8V
H
Operating Temp
None Extended
IT Industrial
Configuration
8 Meg x16
8M16LF
Package
54-ball VFBGA (8mm x 8mm)
54-ball VFBGA (8mm x 8mm) Lead-Free
F4
B4
Speed Grade
-8 8ns
-10 9.6ns
General Description
The Micron® 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 32,554,432-bit banks is organized as 4,096 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless high-speed, random-access opera-
tion.
The 128Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, deep power-down mode. All inputs
and outputs are LVTTL-compatible.
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
128Mb: x16 Mobile SDRAM
Mode Register Definition
Figure 4: Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12 11 10 9 8 7 6 5 4 3
Reserved** Reserved* WB Op Mode CAS Latency BT
2 10
Burst Length
Mode Register (Mx)
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M8 M7 M6-M0
0 0 Defined
--
-
Operating Mode
Standard Operation
All other states reserved
Burst Type
CAS Latency
Note:
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 4, "Burst Definition," on page 10.
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to one,
two, or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT48H8M16LF.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT48H8M16LF | Synchronous DRAM | Micron Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |