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PDF MT48H32M32LG Data sheet ( Hoja de datos )
| Número de pieza | MT48H32M32LG | |
| Descripción | Mobile LPSDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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Mobile LPSDR SDRAM
MT48H32M32LF/LG – 8 Meg x 32 x 4 Banks
1Gb: x32 Mobile LPSDR SDRAM
Features
Features
• VDD/VDDQ = 1.7–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continu-
ous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• 64ms refresh period
Options
• VDD/VDDQ: 1.8V/1.8V
• Addressing
– Standard addressing option
– Reduced page size option1
• Configuration
– 32 Meg x 32 (8 Meg x 32 x 4
banks)
• Plastic “green” packages
– 90-ball VFBGA (8mm x 13mm)
• Timing – cycle time
– 6ns at CL = 3
– 7.5ns at CL = 3
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
• Revision
Marking
H
LF
LG
32M32
B5
-6
-75
None
IT
:B
Note: 1. Contact factory for availability.
Table 1: Configuration Addressing
Architecture
Number of banks
Bank address balls
Row address balls
Column address balls
Note: 1. Contact factory for availability.
32 Meg x 32
4
BA0, BA1
A[12:0]
A[9:0]
32 Meg x 32 Reduced Page Size
Option1
4
BA0, BA1
A[13:0]
A[8:0]
Table 2: Key Timing Parameters
Clock Rate (MHz)
Speed Grade
CL = 2
CL = 3
-6 104 166
-75 104
Note: 1. CL = CAS (READ) latency.
133
CL = 2
8ns
8ns
Access Time
CL = 3
5ns
5.4ns
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
1Gb: x32 Mobile LPSDR SDRAM
Features
List of Tables
Table 1: Configuration Addressing ................................................................................................................... 1
Table 2: Key Timing Parameters ....................................................................................................................... 1
Table 3: VFBGA Ball Descriptions ..................................................................................................................... 9
Table 4: Absolute Maximum Ratings .............................................................................................................. 11
Table 5: DC Electrical Characteristics and Operating Conditions ..................................................................... 11
Table 6: Capacitance ..................................................................................................................................... 12
Table 7: IDD Specifications and Conditions (x32) ............................................................................................. 13
Table 8: IDD7 Specifications and Conditions ( x32) ........................................................................................... 14
Table 9: Electrical Characteristics and Recommended AC Operating Conditions .............................................. 16
Table 10: AC Functional Characteristics ......................................................................................................... 17
Table 11: Target Output Drive Characteristics (Full Strength) ........................................................................... 19
Table 12: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 20
Table 13: Target Output Drive Characteristics (One-Half Strength) .................................................................. 21
Table 14: Truth Table – Commands and DQM Operation ................................................................................. 23
Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 29
Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 31
Table 17: Truth Table – CKE ........................................................................................................................... 33
Table 18: Burst Definition Table ..................................................................................................................... 38
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
5 Page 
1Gb: x32 Mobile LPSDR SDRAM
Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 4: Absolute Maximum Ratings
Voltage/Temperature
Voltage on VDD/VDDQ supply relative to VSS
Voltage on inputs, NC or I/O balls relative to VSS
Storage temperature (plastic)
Symbol
VDD/VDDQ1
VIN
TSTG
Min
–0.5
–0.5
–55
Max
2.4
2.4
150
Units
V
˚C
Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed
VDD.
Table 5: DC Electrical Characteristics and Operating Conditions
Notes 1 and 2 apply to all parameters and conditions; VDD/VDDQ = 1.7–1.95V
Parameter/Condition
Symbol
Min
Max
Units Notes
Supply voltage
I/O supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output high voltage
Output low voltage
Input leakage current:
VDD
VDDQ
VIH
VIL
VOH
VOL
II
1.7
1.7
0.8 × VDDQ
–0.3
0.9 × VDDQ
–
–1.0
1.95
1.95
VDDQ + 0.3
+0.3
–
0.2
1.0
V
V
V
V
V
V
μA
3
3
4
4
Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)
Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ IOZ –1.5 1.5 μA
Operating temperature:
Industrial
TA
–40
85 ˚C
Commercial
TA
0
70 ˚C
Notes:
1. All voltages referenced to VSS.
2. A full initialization sequence is required before proper device operation is ensured.
3. VIH,max overshoot: VIH,max = VDDQ + 2V for a pulse width ≤3ns, and the pulse width can-
not be greater than one- third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse
width ≤3ns.
4. IOUT = 4mA for full drive strength. Other drive strengths require appropriate scale.
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT48H32M32LG.PDF ] | |
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