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PDF MT46H32M16LF Data sheet ( Hoja de datos )
| Número de pieza | MT46H32M16LF | |
| Descripción | Mobile Low-Power DDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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512Mb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H32M16LF – 8 Meg x 16 x 4 banks
MT46H16M32LF – 4 Meg x 32 x 4 banks
MT46H16M32LG – 4 Meg x 32 x 4 banks
Features
• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh, 32ms for automotive temperature
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-5
-54
-6
-75
Clock Rate
200 MHz
185 MHz
166 MHz
133 MHz
Access Time
5.0ns
5.0ns
5.0ns
6.0ns
Options
Marking
• VDD/VDDQ
– 1.8V/1.8V
H
• Configuration
– 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
– 16 Meg x 32 (4 Meg x 32 x 4 banks) 16M32
• Addressing
– JEDEC-standard addressing
– Reduced page size1
LF
LG
• Plastic "green" package
– 60-ball VFBGA (8mm x 9mm)2
– 90-ball VFBGA (8mm x 13mm)3
BF
B5
• Timing – cycle time
– 5ns @ CL = 3 (200 MHz)
-5
– 5.4ns @ CL = 3 (185 MHz)
-54
– 6ns @ CL = 3 (166 MHz)
-6
– 7.5ns @ CL = 3 (133 MHz)
-75
• Power
– Standard IDD2/IDD6
• Operating temperature range
None
– Commercial (0˚ to +70˚C)
None
– Industrial (–40˚C to +85˚C)
IT
– Automotive (–40˚C to +105˚C)
AT
• Design revision
:C
Notes: 1. Contact factory for availability.
2. Only available for x16 configuration.
3. Only available for x32 configuration.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
512Mb: x16, x32 Mobile LPDDR SDRAM
Features
List of Figures
Figure 1: 512Mb Mobile LPDDR Part Numbering .............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11
Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12
Figure 6: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 15
Figure 7: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................. 16
Figure 8: Typical Self Refresh Current vs. Temperature .................................................................................... 25
Figure 9: ACTIVE Command .......................................................................................................................... 37
Figure 10: READ Command ........................................................................................................................... 38
Figure 11: WRITE Command ......................................................................................................................... 39
Figure 12: PRECHARGE Command ................................................................................................................ 40
Figure 13: DEEP POWER-DOWN Command ................................................................................................... 41
Figure 14: Simplified State Diagram ............................................................................................................... 47
Figure 15: Initialize and Load Mode Registers ................................................................................................. 49
Figure 16: Alternate Initialization with CKE LOW ............................................................................................ 50
Figure 17: Standard Mode Register Definition ................................................................................................. 51
Figure 18: CAS Latency .................................................................................................................................. 54
Figure 19: Extended Mode Register ................................................................................................................ 55
Figure 20: Status Read Register Timing ........................................................................................................... 57
Figure 21: Status Register Definition .............................................................................................................. 58
Figure 22: READ Burst ................................................................................................................................... 61
Figure 23: Consecutive READ Bursts .............................................................................................................. 62
Figure 24: Nonconsecutive READ Bursts ........................................................................................................ 63
Figure 25: Random Read Accesses .................................................................................................................. 64
Figure 26: Terminating a READ Burst ............................................................................................................. 65
Figure 27: READ-to-WRITE ............................................................................................................................ 66
Figure 28: READ-to-PRECHARGE .................................................................................................................. 67
Figure 29: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) .................................................... 68
Figure 30: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) .................................................... 69
Figure 31: Data Output Timing – tAC and tDQSCK .......................................................................................... 70
Figure 32: Data Input Timing ......................................................................................................................... 72
Figure 33: Write – DM Operation .................................................................................................................... 73
Figure 34: WRITE Burst ................................................................................................................................. 74
Figure 35: Consecutive WRITE-to-WRITE ....................................................................................................... 75
Figure 36: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75
Figure 37: Random WRITE Cycles .................................................................................................................. 76
Figure 38: WRITE-to-READ – Uninterrupting ................................................................................................. 77
Figure 39: WRITE-to-READ – Interrupting ...................................................................................................... 78
Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 79
Figure 41: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 80
Figure 42: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81
Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 82
Figure 44: Bank Read – With Auto Precharge ................................................................................................... 85
Figure 45: Bank Read – Without Auto Precharge .............................................................................................. 86
Figure 46: Bank Write – With Auto Precharge .................................................................................................. 87
Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 88
Figure 48: Auto Refresh Mode ........................................................................................................................ 89
Figure 49: Self Refresh Mode .......................................................................................................................... 91
Figure 50: Power-Down Entry (in Active or Precharge Mode) ........................................................................... 92
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
5 Page 
Ball Assignments
Figure 4: 60-Ball VFBGA – Top View, x16 only
123
512Mb: x16, x32 Mobile LPDDR SDRAM
Ball Assignments
456789
A
VSS DQ15 VSSQ
B
VDDQ DQ13 DQ14
C
VSSQ DQ11 DQ12
D
VDDQ DQ9 DQ10
E
VSSQ UDQS DQ8
F
VSS UDM NC
G
CKE CK CK#
H
A9 A11 A12
J
A6 A7 A8
K
VSS A4 A5
VDDQ DQ0 VDD
DQ1 DQ2 VSSQ
DQ3 DQ4 VDDQ
DQ5 DQ6 TEST1
DQ7 LDQS VDDQ
A13 LDM VDD
WE# CAS# RAS#
CS# BA0 BA1
A10/AP A0
A1
A2 A3 VDD
Notes: 1. D9 is a test pin that must be tied to VSS or VSSQ in normal operations.
2. Unused address pins become RFU.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
11 Page | ||
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