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PDF AN10935 Data sheet ( Hoja de datos )
| Número de pieza | AN10935 | |
| Descripción | Using SDR/DDR SDRAM memories | |
| Fabricantes | NXP Semiconductors | |
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AN10935
Using SDR/DDR SDRAM memories with LPC32xx
Rev. 2 — 11 October 2010
Application note
Document information
Info Content
Keywords
LPC32x0, LPC32xx, LPC3220, LPC3230, LPC3240, LPC3250, SDR,
SDRAM, DDR
Abstract
This application note covers hardware related issues for interfacing SDR
or DDR SDRAMs to the LPC32xx family microcontroller.
1 page  
NXP Semiconductors
AN10935
Using SDR/DDR SDRAM memories with LPC32xx
Table 1. EMC pins in SRAM, SDR and DDR operating modes
EMC Interface Pin(s)
Static RAM function
SDR SDRAM function
DDR SDRAM function
EMC_A[00] - EMC_A[12]
Address bus, bits 0 to 12 Address bus, bits 0 to 12 Address bus, bits 0 to 12
EMC_A[13]
Address bus, bit 13
Address bus, BA 0
Address bus, BA 0
EMC_A[14]
Address bus, bit 14
Address bus, BA 1
Address bus, BA 1
EMC_A[15] - EMC_A[23]
Address bus, bit 15 to 23
-
-
EMC_D[00] - EMC_D[15]
Data bus, bits 0 to 15
Data bus, bits 0 to 15
Data bus, bits 0 to 15
EMC_D[16]/EMC_DQS0
Data bus, bit 16
Data bus, bit 16
Data strobe, lower byte
EMC_D[17]/EMC_DQS1
Data bus, bit 17
Data bus, bit 17
Data strobe, upper byte
EMC_D[18]/EMC_CLK_N
Data bus, bit 18
Data bus, bit 18
Inverted SDRAM clock
EMC_D[19] - EMC_D[31]
Data bus bits 19 through 31 Data bus bits 19 through 31 P3[12:0]
EMC_OE_N
SRAM Output Enable
-
-
EMC_BLS[0] - EMC_BLS[3]
SRAM byte lane select 0-3
-
-
EMC_CS[0]_N - EMC_CS[3]_N SRAM chip select 0-3
-
-
EMC_WR_N
SRAM write strobe
SDRAM write strobe
SDRAM write strobe
EMC_CLK
- SDRAM clock
SDRAM clock
EMC_CLKIN
- SDRAM clock feedback
-
EMC_CKE
-
SDRAM clock enable
SDRAM clock enable
EMC_DYCS[0]_N,
EMC_DYCS[1]_N
-
SDRAM chip select 0-1
SDRAM chip select 0-1
EMC_CAS_N
-
SDRAM column
SDRAM column
address strobe
address strobe
EMC_RAS_N
- SDRAM row
SDRAM row
address strobe
address strobe
EMC_DQM[0] - EMC_DQM[3]
-
SDRAM byte write mask
SDRAM byte write mask
0 through 3
0 through 3
AN10935
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 October 2010
© NXP B.V. 2010. All rights reserved.
5 of 47
5 Page 
NXP Semiconductors
AN10935
Using SDR/DDR SDRAM memories with LPC32xx
2.6 DDR SDRAM connections
The LPC32x0 EMC supports only a 16-bit wide system DDR SDRAM bus. The system
DDR SDRAM bus may be constructed with:
• one 16-bit wide DDR SDRAM
• two 8-bit wide DDR SDRAMs
Connections to a single x16 DDR SDRAM are shown in Fig 6. Using a single x16 DDR,
the maximum memory for each EMC_DYCS[1:0]_N is 64 MB (32M x 16). A 16-bit
system data bus using two x8 DDR SDRAMs is shown in Fig 7. Using two x8 DDRs, the
maximum memory for each EMC_DYCS[1:0]_N is 128 MB (two 64M x 8). Connections to
a single x16 Mobile DDR SDRAM is shown in Fig 8. Please see the LPC32xx errata
DDR.1 for using a single ended clock with 2.5V DDR, and DDR.2 for routing DQSx to
increase DDR Dx to DQx data output set-up time. The Errata sheet can be found at
http://www.nxp.com/documents/errata_sheet/ES_LPC3250.pdf.
(1) For exceptions to BA[1:0] connected to EMC_A[14:13] respectively, see Section 2.12
Fig 6. DDR x16 device connections
AN10935
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 October 2010
© NXP B.V. 2010. All rights reserved.
11 of 47
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet AN10935.PDF ] | |
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