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PDF ISL8126A Data sheet ( Hoja de datos )
| Número de pieza | ISL8126A | |
| Descripción | Dual/n-Phase Buck PWM Controller | |
| Fabricantes | Intersil | |
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Dual/n-Phase Buck PWM Controller with Integrated
Drivers
ISL8126
The ISL8126 integrates two voltage-mode PWM leading-edge
modulation control with input feed-forward synchronous buck
PWM controllers to control dual independent voltage
regulators or a 2-phase single output regulator. It also
integrates current sharing control for the power module to
operate in parallel, which offers high system flexibility.
The ISL8126 integrates an internal linear regulator, which
generates IC’s bias voltages for applications with only one
single supply rail. The internal oscillator is adjustable from
150kHz to 1.5MHz, and is able to synchronize to an external
clock signal for frequency synchronization and phase
paralleling applications. Its PLL circuit can output a
phase-shift-programmable clock signal for the system to be
expanded to 3-, 4-, 6-, 12- phases with desired interleaving
phase shift.
The ISL8126’s Fault Spreading feature protects any channel
from overloading/stressing due to system faults or phase
failure. The undervoltage fault protection features are also
designed to prevent a negative transient on the output voltage
during falling down. This eliminates the Schottky diode that is
used in some systems for protecting the load device from
reversed output voltage damage.
Table 1 summarizes the differences between ISL8126 and
ISL8126A.
TABLE 1.
DEVICES
ISL8126
ISL8126A
REFERENCE VOLTAGE
(V)
0.6
0.7
VSEN1+ to VSEN1- INPUT
IMPEDANCE
500kΩ
>2MΩ
Features
• Wide VIN Range Operation: 3V to 26.5V
- VCC Operation from 3V to 5.60V
• Excellent Output Voltage Regulation: 0.6V Internal
Reference
• Frequency Synchronization with Programmable Phase Delay
up to 12-Phase Applications
• Fault Spreading Capability for High System Reliability
• Digital Soft-Start with Pre-Charged Output Start-up
Capability
• Dual Independent Channel Enable Inputs with Precision
Voltage Monitor and Voltage Feed-forward Capability
- Programmable Input Voltage POR and its Hysteresis with
a Resistor Divider at EN Input
• Extensive Circuit Protection Functions: Output Overvoltage,
Undervoltage, Overcurrent Protection, Over-temperature and
Pre-Power-On-Reset Overvoltage Protection Option
Applications
• Power Supply for Datacom/Telecom and POL
• Paralleling Power Module
• Wide and Narrow Input Voltage Range Buck Regulators
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
August 16, 2012
FN7892.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Controller Block Diagram
ISL8126
VCC
400mV
ICSH_CORR
VSEN1- 30
VSEN1+ 29
VMON1 31
FB1 32
COMP1 1
EN/VFF1 4
EN_TH
PGOOD
8
PGOOD
CIRCUIT
EN1
EN2
VMON1
VMON2
CH1_FAULT
CH2_FAULT
VCC
26
POWER-ON
RESET
SAW1
VIN
16
INTERNAL
LINEAR REGULATOR
INT. VREF
SS1
E/A
∑
CURRENT
BALANCE
CIRCUIT
PWM1
Ch1 Fault
MOSFET
DRIVER
INT. VREF
EN1
IAVG_CS ICS1 ICSH_ERR
OV/UV
COMP1
CHANNEL 1
SOFT-START AND
FAULT LOGIC
CH1
OCP
7-CYCLE
DELAY
CHPAWNMN1EL 1
CURRENT
SAMPLING
ICS1
111µA
21 PVCC
25 BOOT1
24 UGATE1
23 PHASE1
22 LGATE1
27 ISEN1A
28 ISEN1B
IEN_HYS
FSYNC 5
CLKOUT/
REFIN
7
VCC
400mV
VSEN2- 12
VSEN2+ 13
VMON2 11
FB2 10
COMP2 9
INT. VREF
M/D CONTROL
SS2
AVG_OCP
EN/VFF1 EN/VFF2
SAW1
1.2V
MASTER CLOCK
OSCILLATOR
GENERATOR
ICSH_CORR
M/D CONTROL
CURRENT
SHARE
BLOCK
ICSH_ERR
3 ISHARE
2 ISET
RELATIVE
PHASE
CONTROL
VSEN2+ FB2
ICS1
ICS2
AVERAGE IAVG_CS+15µA
CURRENT
M/D = 1 (Multiphase operation) : IAVG_CS = (ICS1+ICS2) / 2
M/D = 0 (Dual-output Operation) : IAVG_CS = ICS1
PVCC
SAW2
17 BOOT2
E/A
∑
PWM2
MOSFET
DRIVER
18 UGATE2
CURRENT
BALANCE
IAVG_CS Ch2 Fault
ICS2
19 PHASE2
CIRCUIT
ICSH_ERR
20 LGATE2
EN/VFF2 6
EN_TH
INT. VREF
EN2
IEN_HYS
OV/UV
COMP2
CHANNEL 2
SOFT-START AND
FAULT LOGIC
CH2
OCP
AVG_OCP
EP
7-CYCLE
DELAY
111µA
ICS2
CHPAWNMN1EL 2
CURRENT
SAMPLING
M/D CONTROL
15 ISEN2A
14 ISEN2B
5 FN7892.1
August 16, 2012
5 Page 
ISL8126
Typical Application Circuits (Continued)
Double Data Rate I or II
+3.3 TO +26.5V
VIN
CF2
RCC
VCC
CF1
PVCC
BOOT1
VIN
CF3
UGATE1
PHASE1
CHFIN
CBIN
CBOOT1
Q1 LOUT1
RFS FSYNC
ISL8126
VDDQ
R*(VTT/0.6-1)
(Notes 4, 5)
R
CLKOUT/REFIN
1nF
(Or tie REFIN pin to VMON1 pin)
LGATE1
2kΩ
ISEN1A
ISEN1B
Q2
RISEN1
COMP1 ZCOMP1
FB1
VMON1
VSEN1+
VSEN1-
ZFB1
ROS1
RFB1
CSEN1
BOOT2
UGATE2
PHASE2
VDDQ Or VIN
CBOOT2
Q3 LOUT2
PGOOD
RSET
ISET
ISHARE
GND
LGATE2
ISEN2A
ISEN2B
2kΩ
COMP2 ZCOMP1
Q4
RISEN2
FB2
VMON2
VSEN2+
VSEN2-
ZFB1
ROS2
RFB2
CSEN2
2.5V (DDR I)
1.8V (DDR II)
VDDQ
COUT1
10Ω
10Ω
VSENSE1+
VSENSE1-
1.25V (DDR I)
0.9V (DDR II)
COUT2
VTT
( VDDQ/2)
10Ω
10Ω
VSENSE2+
VSENSE2-
NOTES:
4. Setting the upper resistor to be a little higher than R*(VDDQ/0.7 - 1) will set the final REFIN voltage (stead state voltage after soft-start)
derived from the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V
reference after soft-start. The other way is to add more delay at EN/VFF1 pin to have Channel 2 tracking VDDQ (check the “DDR and
Dual Mode Operation” on page 36 for more details).
5. Another way to set REFIN voltage is to connect VMON1 directly to the REFIN pin.
11 FN7892.1
August 16, 2012
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL8126A.PDF ] | |
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