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PDF MT46H128M32L2 Data sheet ( Hoja de datos )
| Número de pieza | MT46H128M32L2 | |
| Descripción | Mobile Low-Power DDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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2Gb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H128M16LF – 32 Meg x 16 x 4 Banks
MT46H64M32LF – 16 Meg x 32 x 4 Banks
MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2
MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4
MT46H256M32R4 – 32 Meg x 16 x 4 Banks x 4
Features
• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh; 32ms for the automotive temperature
range
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-5
-54
-6
-75
Clock Rate
200 MHz
185 MHz
166 MHz
133 MHz
Access Time
5.0ns
5.0ns
5.0ns
6.0ns
Options
Marking
• VDD/VDDQ
– 1.8V/1.8V
• Configuration
– 128 Meg x 16 (32 Meg x 16 x 4 banks)
– 64 Meg x 32 (16 Meg x 32 x 4 banks)
• Addressing
– JEDEC-standard
– Reduced page-size1
– 4-die stack reduced page-size2
– 2-die stack standard
– 4-die stack standard
• Plastic "green" package
– 60-ball VFBGA (10mm x 11.5mm)3
– 90-ball VFBGA (10mm x 13mm)4
• PoP (plastic "green" package)
– 168-ball VFBGA (12mm x 12mm)4
– 168-ball WFBGA (12mm x 12mm)4
– 168-ball WFBGA (12mm x 12mm)4
– 240-ball WFBGA (14mm x 14mm)4
• Timing – cycle time
– 5ns @ CL = 3 (200 MHz)
– 5.4ns @ CL = 3 (185 MHz)
– 6ns @ CL = 3 (166 MHz)
– 7.5ns @ CL = 3 (133 MHz)
• Power
– Standard IDD2/IDD6
• Operating temperature range
– Commercial (0˚ to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)1
• Design revision
H
128M16
64M32
LF
LG
R4
L2
L4
CK
CM
JV
KQ
MA
MC
-5
-54
-6
-75
None
None
IT
AT
:A
Notes:
1. Contact factory for availability.
2. Available in the 168-ball JV package only.
3. Available only for x16 configuration.
4. Available only for x32 configuration.
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
2Gb: x16, x32 Mobile LPDDR SDRAM
Features
List of Figures
Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – Top View, x16 only ................................................................................................. 11
Figure 5: 90-Ball VFBGA – Top View, x32 only ................................................................................................. 12
Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 13
Figure 7: 240-Ball FBGA – 14mm x 14mm (Top View), x32 only ........................................................................ 14
Figure 8: Single Rank, Single Channel (1 Die) Package Block Diagram ............................................................. 17
Figure 9: Dual Rank, Single Channel (2 Die) Package Block Diagram ............................................................... 18
Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram ............................................................. 19
Figure 11: 60-Ball VFBGA (10mm x 11.5mm), Package Code: CK ...................................................................... 20
Figure 12: 90-Ball VFBGA (10mm x 13mm), Package Code: CM ....................................................................... 21
Figure 13: 168-Ball VFBGA (12mm x 12mm), Package Code: JV ........................................................................ 22
Figure 14: 168-Ball WFBGA (12mm x 12mm), Package Code: KQ ..................................................................... 23
Figure 15: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ..................................................................... 24
Figure 16: 240-Ball WFBGA (14mm x 14mm), Package Code: MC ..................................................................... 25
Figure 17: Typical Self Refresh Current vs. Temperature ................................................................................. 34
Figure 18: ACTIVE Command ........................................................................................................................ 46
Figure 19: READ Command ........................................................................................................................... 47
Figure 20: WRITE Command ......................................................................................................................... 48
Figure 21: PRECHARGE Command ................................................................................................................ 49
Figure 22: DEEP POWER-DOWN Command .................................................................................................. 50
Figure 23: Simplified State Diagram ............................................................................................................... 56
Figure 24: Initialize and Load Mode Registers ................................................................................................. 58
Figure 25: Alternate Initialization with CKE LOW ............................................................................................ 59
Figure 26: Standard Mode Register Definition ................................................................................................ 60
Figure 27: CAS Latency .................................................................................................................................. 63
Figure 28: Extended Mode Register ................................................................................................................ 64
Figure 29: Status Read Register Timing .......................................................................................................... 66
Figure 30: Status Register Definition .............................................................................................................. 67
Figure 31: READ Burst ................................................................................................................................... 70
Figure 32: Consecutive READ Bursts .............................................................................................................. 71
Figure 33: Nonconsecutive READ Bursts ........................................................................................................ 72
Figure 34: Random Read Accesses ................................................................................................................. 73
Figure 35: Terminating a READ Burst ............................................................................................................. 74
Figure 36: READ-to-WRITE ............................................................................................................................ 75
Figure 37: READ-to-PRECHARGE .................................................................................................................. 76
Figure 38: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) ................................................... 77
Figure 39: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) ................................................... 78
Figure 40: Data Output Timing – tAC and tDQSCK .......................................................................................... 79
Figure 41: Data Input Timing ......................................................................................................................... 81
Figure 42: Write – DM Operation ................................................................................................................... 82
Figure 43: WRITE Burst ................................................................................................................................. 83
Figure 44: Consecutive WRITE-to-WRITE ....................................................................................................... 84
Figure 45: Nonconsecutive WRITE-to-WRITE ................................................................................................. 84
Figure 46: Random WRITE Cycles .................................................................................................................. 85
Figure 47: WRITE-to-READ – Uninterrupting ................................................................................................. 86
Figure 48: WRITE-to-READ – Interrupting ...................................................................................................... 87
Figure 49: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 88
Figure 50: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 89
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
5 Page 
Ball Assignments
Figure 4: 60-Ball VFBGA – Top View, x16 only
123
2Gb: x16, x32 Mobile LPDDR SDRAM
Ball Assignments
456789
A
VSS DQ15 VSSQ
B
VDDQ DQ13 DQ14
C
VSSQ DQ11 DQ12
D
VDDQ DQ9 DQ10
E
VSSQ UDQS DQ8
F
VSS UDM NC
G
CKE CK CK#
H
A9 A11 A12
J
A6 A7 A8
K
VSS A4 A5
VDDQ DQ0
VDD
DQ1 DQ2 VSSQ
DQ3 DQ4 VDDQ
DQ5 DQ6 TEST1
DQ7 LDQS VDDQ
A13 LDM VDD
WE# CAS# RAS#
CS# BA0 BA1
A10/AP A0
A1
A2 A3 VDD
Notes: 1. D9 is a test pin that must be tied to VSS or VSSQ in normal operations.
2. Unused address pins become RFU.
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
11 Page | ||
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