PDF M470T2864FB3 Data sheet ( Hoja de datos )

Número de pieza	M470T2864FB3
Descripción	200pin Unbuffered SODIMM
Fabricantes	Samsung semiconductor
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No Preview Available ! Rev. 1.2, Oct. 2010 M470T6464FBS M470T2863FB3 M470T2864FB3 M470T5663FB3 200pin Unbuffered SODIMM based on 1Gb F-die 60FBGA/84FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page Unbuffered SODIMM datasheet Rev. 1.2 DDR2 SDRAM 4. Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S1 116 A13 17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 33 VSS 34 VSS 83 NC 84 NC 133 VSS 134 DQ38 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS NOTE :NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules. Pin Front Pin 151 DQ42 152 153 DQ43 154 155 VSS 156 157 DQ48 158 159 DQ49 160 161 VSS 162 163 NC, TEST 164 165 VSS 166 167 DQS6 168 169 DQS6 170 171 VSS 172 173 DQ50 174 175 DQ51 176 177 VSS 178 179 DQ56 180 181 DQ57 182 183 VSS 184 185 DM7 186 187 VSS 188 189 DQ58 190 191 DQ59 192 193 VSS 194 195 SDA 196 197 SCL 198 199 VDDSPD 200 Back DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1 5. Pin Description Pin Name CK0,CK1 CK0,CK1 CKE0,CKE1 RAS CAS WE Description Clock Inputs, positive line Clock Inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable S0,S1 Chip Selects A0~A9, A11~A13 A10/AP BA0,BA1 ODT0,ODT1 SCL CK0,CK1 Address Inputs Address Input/Autoprecharge SDRAM Bank Address On-die termination control Serial Presence Detect(SPD) Clock Input Clock Inputs, positive line NOTE : The VDD and VDDQ pins are tied to the single power-plane on PCB. Pin Name SDA SA1,SA0 DQ0~DQ63 DM0~DM7 DQS0~DQS7 DQS0~DQS7 TEST VDD VSS VREF VDDSPD NC SDA Description SPD Data Input/Output SPD address Data Input/Output Data Masks Data strobes Data strobes complement Logic Analyzer specific test pin (No connect on So-DIMM) Core and I/O Power Ground Input/Output Reference SPD Power Spare pins, No connect SPD Data Input/Output -5- 5 Page Unbuffered SODIMM datasheet Rev. 1.2 DDR2 SDRAM 8. Absolute Maximum DC Ratings Symbol Parameter Rating Units NOTE VDD VDDQ VDDL VIN, VOUT TSTG Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100 V1 V1 V1 V1 °C 1, 2 NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 9. AC & DC Operating Conditions 9.1 Recommended DC Operating Conditions (SSTL - 1.8) Symbol VDD VDDL VDDQ VREF VTT Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Min. 1.7 1.7 1.7 0.49VDDQ VREF-0.04 Rating Typ. 1.8 1.8 1.8 0.50VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V NOTE 4 4 1,2 3 Symbol VDDSPD Parameter Core Supply Voltage Min. 1.7 Rating Max. 3.6 Units V NOTE 5 NOTE : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. 5. SODIMMs that include an optional temperature sensor may require a restricted VDDSPD operating voltage range for proper operation of the temperature sensor. Refer to the thermal sensor specification for details regarding the supported voltage range. All other functions of the SODIMM SPD are supported across the full VDDSPD range. - 11 - 11 Page

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