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PDF MT47H1G4 Data sheet ( Hoja de datos )
| Número de pieza | MT47H1G4 | |
| Descripción | TwinDie DDR2 SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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4Gb: x4, x8 TwinDie DDR2 SDRAM
Features
TwinDie™ DDR2 SDRAM
MT47H1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks
MT47H512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks
Features
• Uses 2Gb Micron die
• Two ranks (includes dual CS#, ODT, and CKE balls)
• Each rank has 8 internal banks for concurrent oper-
ation
• VDD = VDDQ = +1.8V ±0.1V
• JEDEC-standard 63-ball FBGA
• Low-profile package – 1.35mm MAX thickness
Functionality
The 4Gb (TwinDie™) DDR2 SDRAM uses Micron’s
2Gb DDR2 monolithic die and has similar functionali-
ty. This TwinDie data sheet is intended to provide a
general description, package dimensions, and the
ballout only. Refer to Micron's 2Gb DDR2 data sheet
for complete information or for specifications not in-
cluded in this document.
Options
• Configuration
– 64 Meg x 4 x 8 banks x 2 ranks
– 32 Meg x 8 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 63-ball FBGA (9mm x 11.5mm) Rev.
C
• Timing – cycle time1
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C)
• Revision
Note: 1. CL = CAS (READ) latency.
Marking
1G4
512M8
WTR
-25E
-25
-3
-37E
None
None
:C
Table 1: Key Timing Parameters
Speed
Grade
-25E
-25
-3
-37E
CL = 3
400
400
400
400
Data Rate (MT/s)
CL = 4 CL = 5
533 800
533 667
533 667
533 n/a
CL = 6
800
800
n/a
n/a
tRCD (ns)
12.5
15
15
15
tRP (ns)
12.5
15
15
15
tRC (ns)
55
55
55
55
tRFC (ns)
197.5
197.5
197.5
197.5
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
1 Gig x 4
64 Meg x 4 x 8 banks x 2 ranks
8K
A[14:0] (32K)
BA[2:0] (8)
A[11, 9:0] (2K)
512 Meg x 8
32 Meg x 8 x 8 banks x 2 ranks
8K
A[14:0] (32K)
BA[2:0] (8)
A[9:0] (1K)
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
4Gb: x4, x8 TwinDie DDR2 SDRAM
Functional Description
Functional Description
The 4Gb (TwinDie) DDR2 SDRAM is a high-speed, CMOS dynamic random access
memory device containing 4,294,967,296 bits and internally configured as two 8-bank
2Gb DDR2 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
Each DDR2 SDRAM die uses a double data rate architecture to achieve high-speed op-
eration. The DDR2 architecture is essentially a 4n-prefetch architecture, with an inter-
face designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 4n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
Addressing of the TwinDie is identical to the monolithic device. Additionally, multiple
chip selects select the desired rank.
This TwinDie data sheet is intended to provide a general description, package dimen-
sions, and the ballout only. Refer to the Micron 2Gb DDR2 data sheet for complete in-
formation regarding individual die initialization, register definition, command descrip-
tions, and die operation.
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
5 Page 
4Gb: x4, x8 TwinDie DDR2 SDRAM
Electrical Specifications – ICDD Parameters
Table 7: DDR2 IDD Specifications and Conditions (Die Revision C) (Continued)
Notes: 1–8 apply to the entire table
Parameter/Condition
Burst refresh current:tCK = tCK (IDD); refresh command at
every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching (inactive die is in
IDD2P condition, but with inputs switching)
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are floating; Data bus inputs
are floating
Operating bank interleave read current: All bank inter-
leaving reads, Iout = 0mA; BL = 4, CL = CL (IDD), AL = tRCD
(IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD =
tRRD (IDD), tRCD = tRCD (Idd); CKE is HIGH, CS# is HIGH be-
tween valid commands; address bus inputs are stable during
deselects; Data bus inputs are switching (inactive die is in
IDD2P condition, but with inputs switching)
Com-
bined
Symbol
ICDD5
ICDD6
ICDD7
Individual
Die Status
ICDD5 =
IDD5 + ICDD2P
Bus
Width
x4, x8
ICDD6 =
IDD6 + IDD6
x4, x8
ICDD7 =
IDD7 + ICDD2P
x4, x8
-25E/
-25
197
24
262
-3E/-3 Units
177 mA
24 mA
237 mA
Notes:
1. ICDD/IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
VDD = VDDQ = +1.8V ±0.1V; VDDL = +1.8V ±0.1V; VREF = VDDQ/2.
2. ICDD/IDD parameters are specified with ODT disabled.
3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#. Idd values must be met
with all combinations of EMR bits 10 and 11.
4. ICDD/IDDvalues must be met with all combinations of EMR bits 10 and 11.
5. Definitions for ICDD/IDD conditions:
LOW
VIN(AC) ≤ VIL(AC)max
HIGH
Stable
VIN ≥ VIH(AC)min
Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. ICDD values reflect the combined current of both individual die. IDDx represents individual
die values.
8. The following IDD values must be derated (IDD limits increase) on IT-option or on AT-op-
tion devices when operated outside of the range 0°C ≤ TC ≤ 85°C:
When IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derat-
TC ≤ 0°C ed by 2%; and IDD6 and IDD7 must be derated by 7%
When
IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be de-
TC ≥ 85°C rated by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
11 Page | ||
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