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PDF MT42L64M64D2 Data sheet ( Hoja de datos )
| Número de pieza | MT42L64M64D2 | |
| Descripción | Mobile LPDDR2 SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Mobile LPDDR2 SDRAM
MT42L128M16D1, MT42L64M32D1, MT42L64M64D2,
MT42L128M32D2, MT42L256M32D4, MT42L128M64D4
MT42L96M64D3, MT42L192M32D3
Features
• Ultra low-voltage core and I/O power supplies
– VDD2 = 1.14–1.30V
– VDDCA/VDDQ = 1.14–1.30V
– VDD1 = 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed
Grade
-182
-25
-3
Clock
Rate
(MHz)
533
400
333
Data Rate
(Mb/s/pin) RL WL tRCD/tRP1
1066
8 4 Typical
800 6 3 Typical
667 5 2 Typical
Options
• VDD2: 1.2V
• Configuration
– 16 Meg x 16 x 8 banks x 1 die
– 8 Meg x 32 x 8 banks x 1 die
– 8 Meg x 32 x 8 banks x 2 die
– 16 Meg x 16 x 8 banks x 4 die
– 8 Meg x 32 x 8 banks x 2 die
– 8 Meg x 32 x 8 banks x 3 die
– 8 Meg x 32 x 8 banks x 4 die
– 16 Meg x 16 x 8 banks x 2 die +
8 Meg x 32 x 8 banks x 1 die
• Device type
– LPDDR2-S4, 1 die in package
– LPDDR2-S4, 2 die in package
– LPDDR2-S4, 3 die in package
– LPDDR2-S4, 4 die in package
• FBGA“green” package
– 134-ball FBGA (11mm x 11.5mm)
– 134-ball FBGA (11.5mm x 11.5mm)
– 168-ball FBGA (12mm x 12mm)
– 168-ball FBGA (12mm x 12mm)
– 168-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 220-ball FBGA (14mm x 14mm)
– 220-ball FBGA (14mm x 14mm)
• Timing – cycle time
– 1.875ns @ RL = 8
– 2.5ns @ RL = 6
– 3.0ns @ RL = 5
• Operating temperature range
– From –25°C to +85°C
– From –40°C to +105°C
• Revision
Marking
L
128M16
64M32
128M32
256M32
64M64
96M64
128M64
192M32
D1
D2
D3
D4
MH
MG
KL
LE
KP
KH
KJ
KU
MP
LD
-182
-25
-3
IT
AT
:A
Notes: 1. For fast tRCD/tRP, contact factory.
2. For -18 speed grade, contact factory.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Input/Output Capacitance ......................................................................................................................... 113
Electrical Specifications – IDD Specifications and Conditions ........................................................................... 114
AC and DC Operating Conditions ................................................................................................................... 117
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 119
VREF Tolerances ......................................................................................................................................... 120
Input Signal .............................................................................................................................................. 121
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 123
Single-Ended Requirements for Differential Signals .................................................................................... 124
Differential Input Crosspoint Voltage ......................................................................................................... 126
Input Slew Rate ......................................................................................................................................... 127
Output Characteristics and Operating Conditions ........................................................................................... 127
Single-Ended Output Slew Rate .................................................................................................................. 128
Differential Output Slew Rate ..................................................................................................................... 129
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 131
Output Driver Impedance .............................................................................................................................. 131
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 132
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 133
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 133
Clock Specification ........................................................................................................................................ 137
tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 138
Clock Period Jitter .......................................................................................................................................... 138
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 138
Cycle Time Derating for Core Timing Parameters ........................................................................................ 139
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 139
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 139
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 139
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 140
Refresh Requirements .................................................................................................................................... 141
AC Timing ..................................................................................................................................................... 142
CA and CS# Setup, Hold, and Derating ........................................................................................................... 149
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 156
Revision History ............................................................................................................................................ 163
Rev. N, Production – 3/12 ........................................................................................................................... 163
Rev. M, Production – 10/11 ........................................................................................................................ 163
Rev. L, Production – 09/11 .......................................................................................................................... 163
Rev. K, Production – 08/11 ......................................................................................................................... 163
Rev. J, Production – 05/11 .......................................................................................................................... 163
Rev. H, Production – 3/11 ........................................................................................................................... 163
Rev. G, Production – 1/11 ........................................................................................................................... 163
Rev. F, Advance – 11/10 .............................................................................................................................. 163
Rev. E, Advance – 09/10 .............................................................................................................................. 163
Rev. D, Advance – 07/10 ............................................................................................................................. 163
Rev. C, Advance – 07/10 ............................................................................................................................. 164
Rev. B, Advance – 03/10 .............................................................................................................................. 164
Rev. A, Advance – 03/10 .............................................................................................................................. 164
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
5 Page 
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
General Description
General Description
The 2Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic
random-access memory containing 2,147,483,648 bits. The LPDDR2-S4 device is inter-
nally configured as an eight-bank DRAM. Each of the x16’s 268,435,456-bit banks is or-
ganized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit
banks is organized as 16,384 rows by 512 columns by 32 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter-
preted as any or all DQ collectively, unless specifically stated otherwise.
“DQS” and “CK” should be interpreted as DQS, DQS# and CK, CK# respectively, unless
specifically stated otherwise. “BA” includes all BA pins used for a given density.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
11 Page | ||
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