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PDF MT41K256M4 Data sheet ( Hoja de datos )
| Número de pieza | MT41K256M4 | |
| Descripción | 1.35V DDR3L SDRAM Addendum | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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Preliminary‡
1Gb: x4, x8 DDR3L SDRAM Addendum
Description
1.35V DDR3L SDRAM Addendum
MT41K256M4 – 32 Meg x 4 x 8 banks
MT41K128M8 – 16 Meg x 8 x 8 banks
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 SDRAM (1.5V). Unless stated otherwise, DDR3L
SDRAM meet the functional and timing specifications
listed in the equivalent density DDR3 SDRAM data
sheet located on www.micron.com.
Features
• VDD = VDDQ = +1.35V (1.283V to 1.45V)
• Backward-compatible to VDD = VDDQ = +1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• CAS (READ) latency (CL): 6, 7, or 8
• Posted CAS additive latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options1
• Configuration
– 256 Meg x 4
– 128 Meg x 8
• FBGA package (Pb-free) – x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev. F
• Timing – cycle time
– 1.875ns @ CL = 7 (DDR3-1066)
– 1.5ns @ CL = 9 (DDR3-1333)
• Revision
Marking
256M4
128M8
JP
-187E
-15E
:F
Note:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-187E
-15E1
Data Rate (MT/s)
1066
1333
Target tRCD-tRP-CL (ns)
7-7-7
9-9-9
Note: 1. Backward compatible to 1066, CL = 7 (-187E).
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
256 Meg x 4
32 Meg x 4 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
2K A[11, 9:0]
tRCD (ns)
13.1
13.5
tRP (ns)
13.1
13.5
CL (ns)
13.1
13.5
128 Meg x 8
16 Meg x 8 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
1K A[9:0]
PDF: 09005aef833b7221
1Gb_1_35V_DDR3.pdf - Rev. D 4/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
1 page  
Package Dimensions
Figure 2: 78-Ball FBGA – x4, x8; Die Rev. F, “JP”
Preliminary
1Gb: x4, x8 DDR3L SDRAM Addendum
Package Dimensions
Seating
plane
0.12 A
A
0.8 ±0.1
78X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.33
NSMD ball pads.
8 ±0.15
987
321
0.8 TYP
9.6
CTR
Ball A1 ID
A
B
C
D
E
F
G 11.5 ±0.15
H
J
K
L
M
N
0.8
TYP 6.4 CTR
Note: 1. All dimensions are in millimeters.
Ball A1 ID
1.2 MAX
0.25 MIN
PDF: 09005aef833b7221
1Gb_1_35V_DDR3.pdf - Rev. D 4/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
5 Page 
Preliminary
1Gb: x4, x8 DDR3L SDRAM Addendum
Electrical Specifications
Table 16: Single-Ended Output Driver Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Parameter/Condition
Symbol
Output slew rate: Single-ended; For rising and falling
edges, measure between VOL(AC) = VREF - 0.09 × VDDQ
and VOH(AC) = VREF +0.09 × VDDQ
SRQse
Min
1.75
Max
6
Units
V/ns
Table 17: Differential Output Driver Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Parameter/Condition
Symbol
Min
Output slew rate: Differential; For rising and falling
edges, measure between VOL,diff(AC) = –0.18 × VDDQ and
VOH,diff(AC) = +0.18 × VDDQ
Output differential crosspoint voltage
SRQdiff
VOX(AC)
3.5
VREF - 135
Max
12
VREF + 135
Units
V/ns
mV
Table 18: Electrical Characteristics and AC Operating Conditions
Parameter
Data setup time to Base
DQS, DQS#
(specification)
Data setup time to
DQS, DQS#
VREF @ 1 V/ns
Base
(specification)
VREF @ 1 V/ns
Data hold time from Base
DQS, DQS#
(specification)
VREF @ 1 V/ns
CTRL, CMD, ADDR
setup to CK, CK#
CTRL, CMD, ADDR
setup to CK, CK#
CTRL, CMD, ADDR
hold from CK, CK#
Base
(specification)
VREF @ 1 V/ns
Base
(specification)
VREF @ 1 V/ns
Base
(specification)
VREF @ 1 V/ns
DDR3L-800
Symbol Min
Max
DQ Input Timing
tDS AC160 90
–
DDR3L-1066
Min
Max
40 –
250 – 200 –
tDS AC135 140
–
90
–
275 – 225 –
tDH DC90 160 – 110 –
250 – 200
Command and Address Timing
tIS AC160 215 – 140
–
–
375 – 300 –
tIS AC135 365 – 290 –
500 – 425 –
tIH DC90 285 – 210 –
375 – 300 –
DDR3L-1333
Min
Max
Units
n/a –
n/a –
45 –
180 –
75 –
165 –
ps
ps
ps
ps
ps
ps
80 –
240 –
205 –
340 –
150 –
240 –
ps
ps
ps
ps
ps
ps
PDF: 09005aef833b7221
1Gb_1_35V_DDR3.pdf - Rev. D 4/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MT41K256M4.PDF ] | |
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