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PDF PTN3460 Data sheet ( Hoja de datos )
| Número de pieza | PTN3460 | |
| Descripción | eDP to LVDS bridge IC | |
| Fabricantes | NXP Semiconductors | |
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PTN3460
eDP to LVDS bridge IC
Rev. 4 — 12 March 2014
Product data sheet
1. General description
PTN3460 is an (embedded) DisplayPort to LVDS bridge device that enables connectivity
between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes
the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and
transmits processed stream in LVDS format.
PTN3460 has two high-speed ports: Receive port facing DP Source (for example,
CPU/GPU/chip set), Transmit port facing the LVDS receiver (for example., LVDS display
panel controller). The PTN3460 can receive DP stream at link rate 1.62 Gbit/s or
2.7 Gbit/s and it can support 1-lane or 2-lane DP operation. It interacts with DP source via
DP Auxiliary (AUX) channel transactions for DP link training and setup.
It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or
24 bits per pixel and pixel clock frequency up to 112 MHz. The LVDS data packing can be
done either in VESA or JEIDA format. Also, the DP AUX interface transports
I2C-over-AUX commands and support EDID-DDC communication with LVDS panel. To
support panels without EDID ROM, the PTN3460 can emulate EDID ROM behavior
avoiding specific changes in system video BIOS.
PTN3460 provides high flexibility to optimally fit under different platform environments. It
supports three configuration options: multi-level configuration pins, DP AUX interface, and
I2C-bus interface.
PTN3460 can be powered by either 3.3 V supply only or dual supplies (3.3 V/1.8 V) and is
available in the HVQFN56 7 mm 7 mm package with 0.4 mm pitch.
2. Features and benefits
2.1 Device features
Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility
in firmware updates
LVDS panel power-up (/down) sequencing control
Firmware controlled panel power-up (/down) sequence timing parameters
No external timing reference needed
EDID ROM emulation to support panels with no EDID ROM
Supports EDID structure v1.3
On-chip EDID emulation up to seven different EDID data structures
eDP complying PWM signal generation or PWM signal pass through from eDP source
1 page  
NXP Semiconductors
7. Pinning information
7.1 Pinning
PTN3460
eDP to LVDS bridge IC
terminal 1
index area
AUX_N 1
AUX_P 2
GND 3
DP0_P 4
DP0_N 5
VDD(1V8) 6
DP1_P 7
DP1_N 8
RST_N 9
PD_N 10
HPDRX 11
DEV_CFG 12
VDD(3V3) 13
VDD(3V3) 14
(1)
PTN3460BS
42 LVSAE_N
41 LVSAE_P
40 LVSBE_N
39 LVSBE_P
38 VDD(3V3)
37 LVSCE_N
36 LVSCE_P
35 LVSCKE_N
34 LVSCKE_P
33 PVCCEN
32 LVSDE_N
31 LVSDE_P
30 DDC_SDA
29 DDC_SCL
002aaf833
Transparent top view
(1) Center pad is connected to PCB ground plane for electrical grounding and thermal relief.
Fig 3. Pin configuration for HVQFN56
Refer to Section 13 “Package outline” for package and pin dimensions.
PTN3460
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 32
5 Page 
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
The VESA and JEIDA data format definitions are described in Table 7 to Table Table 13.
Table 7. LVDS single bus, 18 bpp, VESA or JEIDA data packing
Channel
Bit position
6543210
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
Table 8. LVDS single bus, 24 bpp, VESA data packing
Channel
Bit position
6543210
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS odd differential channel D
don’t care bit 7
bit 6
bit 7
bit 6
bit 7
bit 6
Table 9. LVDS dual bus, 18 bpp, VESA data packing
Channel
Bit position
6543210
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel A bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS even differential channel B bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS even differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
Table 10. LVDS dual bus, 24 bpp, VESA data packing
Channel
Bit position
6543210
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS odd differential channel D
don’t care bit 7
bit 6
bit 7
bit 6
bit 7
bit 6
LVDS even differential channel A bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS even differential channel B bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS even differential channel C
DE
VSYNC HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel D don’t care bit 7 bit 6 bit 7 bit 6 bit 7 bit 6
PTN3460
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PTN3460.PDF ] | |
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