AND8353 Datasheet PDF - ON Semiconductor
| Part Number | AND8353 | |
| Description | Implementing Cost Effective and Robust Power Factor Correction | |
| Manufacturers | ON Semiconductor | |
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AND8353/D
Implementing Cost
Effective and Robust Power
Factor Correction with the
NCP1607
Prepared by: Alan Finkel
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Introduction
The NCP1607 is a voltage mode power factor correction
(PFC) controller designed to drive cost−effective converters
to meet input line harmonic regulations. The device operates
in Critical Conduction Mode (CRM) for optimal
performance in applications up to about 300 W. Its voltage
mode scheme enables it to obtain unity power factor without
the need for a line sensing network. The output voltage is
accurately controlled with a built in high precision error
amplifier. The controller also implements a comprehensive
array of safety features for robust designs.
This application note describes the design and
implementation of a 400 V, 100 W, CRM Boost PFC
converter using the NCP1607. The converter exhibits high
power factor, low standby power dissipation, high active
mode efficiency, and a variety of protection features.
The Need for PFC
Most electronic ballasts and switching power supplies use
a diode bridge rectifier and a bulk storage capacitor to
produce a dc voltage from the utility ac line. This produces
a non−sinusoidal current draw and increases the demand on
the power delivery infrastructure. Government regulations
and utility requirements often necessitate control over line
current harmonic content.
Active PFC circuits have become the most popular way to
meet these harmonic content requirements. They consist of
inserting a PFC pre−regulator between the rectifier bridge
and the bulk capacitor (Figure 1). The boost (or step−up)
converter is the most popular topology for active power
factor correction. With the proper control, it can be made to
produce a constant output voltage while maintaining a
sinusoidal input current from the line.
Rectifiers
PFC Preconverter
Converter
AC Line
High
+ Frequency
Bypass
Capacitor
NCP1607
+ Bulk
Storage
Capacitor
Load
Figure 1. Active PFC Stage with the NCP1607
Basic Operation of a CRM Boost Converter
For medium power (<300 W) applications, critical
conduction mode (CRM) is the preferred control method.
Critical conduction mode occurs at the boundary between
discontinuous conduction mode (DCM) and continuous
conduction mode (CCM). In CRM, the next driver on time
is initiated when the boost inductor current reaches zero.
Hence, CRM combines the lower peak currents of CCM
operation with the zero current switching of DCM
operation. This control method causes the frequency to vary
with the line input voltage and the output load. The operation
and waveforms of a PFC boost converter are illustrated in
Figure 2. For detailed information on the operation of a
CRM Boost Converter for PFC applications, please refer to
AND8123 at www.onsemi.com.
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 0
1
Publication Order Number:
AND8353/D
|
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AND8353/D
NB
VIN
NZCD
RZCD
RS
ZCD
VDD
VACcLt(iNvEeG)
Clamp
VCCLla(PmOpS)
+
−
VZCDH
+
−
VZCDL
DRIVE
−
+
VSDL
Shutdown
SResetQ
Dominant
Latch
RQ
Demag
Figure 5. ZCD Winding and Internal Logic Arrangement
A turns ratio of 10 is selected for this design. RZCD is
added between the ZCD winding and pin 5 to limit the
current into or out of the pin. This current must be low
enough so as to not trigger the ZCD shutdown feature. RZCD
is calculated using Equation 8:
RZCD
w
VacHL @ Ǹ2
ICL(NEG) @ (NB : NZCD)
+
15.0
kW
(eq. 8)
where ICL(NEG) = 2.5 mA (from the NCP1607 datasheet)
The value of RZCD and the small parasitic capacitance of
the ZCD pin determines when the ZCD winding signal is
detected and the next drive pulse begins. Ideally RZCD turns
on the drive at the drain voltage valley to minimize
switching losses. The value of RZCD large cause minimum
drain voltage switching is fournd experimentally. Too large
of a value creates a significant delay in detecting the ZCD
event. In this case, the controller operates in discontinuous
conduction mode (DCM) and the power factor is reduced. If
RZCD is too small, then the next driver on time starts when
the voltage is high and switching efficiency is reduced.
DESIGN STEP 5: Set the FB, OVP, and UVP Levels
The low bandwidth of the PFC stage causes overshoots
during transient loads or at startup. The NCP1607
incorporates an adjustable overvoltage protection (OVP)
circuit to protect against overshoots. The OVP activation
level is set by ROUT1. A derivation in the NCP1607
datasheet results in Equation 9:
VOUT(OVP) + VOUT(OVP) ) ROUT1 @ IOVP (eq. 9)
Where IOVP = 10 mA.
ROUT1 is calculated using Equation 10:
ROUT1
+
VOUT(OVP) *
IOVP
VOUT
(eq. 10)
ROUT1 is equal to 4.0 MW.
ROUT2 is sized to maintain 2.5 V on the FB pin when Vout
is at the targeted level. The FPP feature introduces an error
into the output voltage.
The output voltage including the error casued by RFB
(VOUT) is calculated using Equation 11.
VOUT
+
VOUT
)
ROUT1
@
VREF
RFB
(eq. 11)
VOUT
+
400
)
4
M
@
2.5
4.7 M
+
402
V
The error caused by RFB is compensated by adjusting
ROUT2. The parallel combination of RFB and ROUT2 form an
equivalent resistor REQ that is calculated using Equation 12.
REQ
+
ROUT1
@
VREF
VOUT * VREF
(eq. 12)
REQ
+
4
M
@
2.5
400 *
2.5
+
25.16
kW
REQ is used to calculate ROUT2.
ROUT2
+
REQ @
RFB *
RFB
REQ
(eq. 13)
ROUT2
+
25.16 k @ 4.7 M
4.7 M * 25.16 k
+
25.29
kW
For this design, a 25.5 kW resistor is used for ROUT2. The
compensated output voltage is calculated using Equation 14.
VOUT
+
VREF
@
ROUT1 ) ROUT2
ROUT2
)
ROUT1
@
VREF
RFB
(eq. 14)
VOUT
+
2.5
@
4
M ) 25.5
25.5 k
k
)
4
M
@
2.5
4.7 M
+
397
V
http://onsemi.com
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| Information | Total 23 Pages | |
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