PDF P3041 Data sheet ( Hoja de datos )

Número de pieza	P3041
Descripción	QorIQ Integrated Processor
Fabricantes	Freescale Semiconductor
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No Preview Available ! Freescale Semiconductor Data Sheet: Technical Data P3041 QorIQ Integrated Processor Hardware Specifications Document Number: P3041EC Rev. 2, 02/2013 P3041 FC-PBGA–1295 37.5 mm x 37.5 mm The P3041 QorIQ integrated processor utilizes four processor cores built on Power Architecture® technology. The cores include high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The chip includes the following functions and features: • Four e500mc Power Architecture cores, each with a backside 128 KB L2 cache with ECC – Three levels of instructions: User, supervisor, and hypervisor – Independent boot and reset – Secure boot capability • CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet end-points • CoreNet platform cache with ECC • CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces • One 10-Gigabit Ethernet (XAUI) controller • Five 1-Gigabit Ethernet controllers – SGMII interfaces — 2.5 Gbps SGMII interfaces – RGMII interfaces • One 64-bit DDR3 SDRAM memory controller with ECC • Multicore programmable interrupt controller • Four I2C controllers • Four 2-pin UARTs or two 4-pin UARTs • Two 4-channel DMA engines • Enhanced local bus controller (eLBC) • Four PCI Express 2.0 controllers/ports • Two serial RapidIO® controllers/ports (sRIO port) supporting version 1.3 with features from 2.1 • Two serial ATA (SATA 2.0) controllers • Enhanced secure digital host controller (SD/MMC) • Enhanced serial peripheral interfaces (eSPI) • 2× high-speed USB 2.0 controllers with integrated PHYs © 2010–2013 Freescale Semiconductor, Inc. All rights reserved. 1 page Pin Assignments and Reset States 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV MDQ MDQ MDM MDQ GND [A2] [A3] [A4] [A5] [A6] [A7] [A8] [A9] [A10] [A11] [A12] [A13] [3] [6] [0] [0] [24] B RSRV GVDD RSRV RSRV [B1] [1] [B3] [B4] GND [2] RSRV RSRV GVDD RSRV RSRV [B6] [B7] [2] [B9] [B10] GND [7] RSRV RSRV GVDD MDQ [B12] [B13] [3] [7] MDQS [0] MDQ [5] GND [31] C RSRV RSRV GND [C] [C2] [1] RSRV RSRV GVDD RSRV [C4] [C5] [6] [C7] MDQ [16] GND [6] MDQ [21] MDQ GVDD RSRV MDQ [20] [5] [C13] [2] GND MDQS MDQ GVDD [14] [0] [4] [4] D RSRV RSRV RSRV GVDD RSRV RSRV [D1] [D2] [D3] [7] [D5] [D6] GND MDQS MDQS GVDD MDM [5] [2] [2] [8] [2] MDQ [17] GND [13] MDM [1] MDQ GVDD MDQ [8] [9] [1] NC [D18] E RSRV GVDD RSRV RSRV GND [E1] [12] [E3] [E4] [4] MDQ [22] MDQ GVDD MDQ [23] [11] [18] MDQ [19] GND [12] MDQ [10] MDQ GVDD MDQ [14] [10] [13] NC [E16] GND [25] LAD [28] F RSRV RSRV GND RSRV RSRV GVDD MDQ MDQ GND MDQ MDQ GVDD MDQ MDQS GND MDQ LAD LAD [F1] [F2] [3] [F4] [F5] [13] [24] [29] [11] [28] [25] [14] [15] [1] [36] [12] [31] [29] G RSRV RSRV RSRV GVDD RSRV RSRV GND MDQS MDQS GVDD MDM MDQ [G1] [G2] [G3] [16] [G5] [G6] [10] [3] [3] [17] [3] [11] GND MDQS MDQ GVDD GND [35] [1] [9] [18] [231] LA [31] H RSRV GVDD RSRV RSRV GND RSRV MDQ GVDD MDQ MDQ [H1] [21] [H3] [H4] [9] [H6] [30] [20] [31] [26] GND NC NC GVDD NC [37] [H12] [H13] [19] [H15] LDP [3] LDP BVDD [2] [9] J RSRV RSRV GND [J1] [J2] [8] RSRV MECC GVDD MECC MECC GND [J4] [1] [22] [5] [4] [38] MDQ [27] NC [J11] GVDD NC [25] [J13] NC [J14] LAD [30] LWE [2] LAD [15] LAD [13] K RSRV RSRV RSRV GVDD MDQS MDQS GND [K1] [K2] [K3] [24] [8] [8] [39] MDM MECC GVDD NC [8] [0] [23] [K11] NC [K12] NC [K13] NC [K14] LWE SENSE- SENSE- LAD [3] VDD_CA GND_CA [14] _PL _PL L RSRV GVDD RSRV RSRV GND [L1] [25] [L3] [L4] [40] MA [15] MECC [6] GVDD [26] MECC [7] MECC VDD [2] _CA_PL [1] GND [230] VDD _CA_PL [2] GND [141] VDD _CA_PL [3] GND [98] VDD _CA_PL [4] GND [32] M RSRV RSRV GND RSRV RSRV GVDD MA [M1] [M2] [41] [M4] [M5] [27] [14] MBA [2] GND [45] MECC [3] GND [113] VDD _CA_PL [9] GND [127] VDD _CA_PL [10] GND [142] VDD _CA_PL [11] GND [157] VDD _CA_PL [12] N RSRV RSRV RSRV GVDD RSRV [N1] [N2] [N3] [28] [N5] MA [12] GND [44] MAPAR_ MCKE ERR [3] GVDD [29] VDD _CA_PL [17] GND [126] VDD _CA_PL [19] GND VDD [N14] _CA_PL [19] GND [156] VDD _CA_PL [20] GND 160] P RSRV GVDD RSRV RSRV GND [P1] [31] [P3] [P4] [43] MA [9] MA [11] GVDD MCKE MCKE [30] [2] [0] GND [113] VDD _CA_PL [26] GND [128] VDD _CA_PL [27] GND [P15] VDD _CA_PL [28] GND [P17] VDD _CA_PL [29] R RSRV RSRV GND RSRV RSRV GVDD MA [R1] [R2] [42] [R4] [R5] [32] [8] MA [7] GND [47] MCKE [1] VDD _CA_PL [34] GND [125] VDD _CA_PL [35] GND [139] VDD _CA_PL [36] GND VDD [155] _CA_PL [37] GND [161] T RSRV RSRV RSRV GVDD RSRV MDIC [T1] [T2] [T3] [34] [T5] [0] GND [48] MA [5] MA [6] GVDD [33] GND [115] VDD _CA_PL [43] GND [129] VDD _CA_PL [44] GND [144] VDD _CA_PL [45] GND [159] VDD _CA_PL [46] U RSRV GVDD GND RSRV GND [U1] [36] [50] [U4] [49] MA [1] MA GVDD MA [2] [37] [3] MA [4] VDD _CA_PL [51] GND [124] VDD _CA_PL [52] GND [138] VDD _CA_PL [53] GND [154] VDD _CA_PL [54] GND [162] V RSRV RSRV RSRV RSRV [V1] [V2] [V3] [V4] MCK [1] MCK GVDD MCK [1] [38] [2] MCK [2] GND [54] GND [116] VDD _CA_PL [60] GND [130] VDD _CA_PL [61] GND [145] VDD _CA_PL [62] GND [222] VDD _CA_PL [63] Figure 3. 1295 BGA Ball Map Diagram (Detail View A) P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 5 5 Page Signal MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 MAPAR_ERR MAPAR_OUT MDM0 MDM1 MDM2 MDM3 MDM4 MDM5 MDM6 MDM7 MDM8 MDQS0 MDQS1 MDQS2 MDQS3 MDQS4 MDQS5 MDQS6 MDQS7 MDQS8 MDQS0 MDQS1 MDQS2 MDQS3 MDQS4 MDQS5 MDQS6 Pin Assignments and Reset States Table 1. Pins List by Bus (continued) Signal Description Error Correcting Code Error Correcting Code Error Correcting Code Error Correcting Code Error Correcting Code Error Correcting Code Error Correcting Code Address Parity Error Address Parity Out Data Mask Data Mask Data Mask Data Mask Data Mask Data Mask Data Mask Data Mask Data Mask Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Data Strobe Package Pin Pin Number Type J5 L10 M10 J8 J7 L7 L9 N8 Y7 A16 D14 D11 G11 AD7 AH8 AL11 AT10 K8 C16 G14 D9 G9 AD5 AH6 AM10 AT12 K6 B16 F14 D8 G8 AD4 AH5 AM9 I/O I/O I/O I/O I/O I/O I/O I O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes — — — — — — — 4 — — — — — — — — — — — — — — — — — — — — — — — — — — P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 11 11 Page

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