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PDF PFP4N60 Data sheet ( Hoja de datos )
| Número de pieza | PFP4N60 | |
| Descripción | N-channel MOSFET | |
| Fabricantes | PowerGate | |
| Logotipo |  |
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PFP4N60/PFF4N60
Features
■ High ruggedness
■ RDS(ON) (Max 2.3 Ω)@VGS=10V
■ Gate Charge (Typ. 27nC)
■ Improved dv/dt Capability
■ 100% Avalanche Tested
PFF4N60
PFP4N60
1
2
3
12
3
1. Gate 2. Drain 3. Source
N-channel MOSFET
BVDSS : 600V
ID : 4.5A
RDS(ON) : 2.3ohm
2
1
General Description
These N-channel enhancement mode field effect power transistor is using Powergate
semiconductor’s advanced planar stripe, DMOS technology intended for off line switch
mode power supply. Also, especially designed to minimize RDS(ON) and high rugged
avalanche characteristics. These devices are well suited for high efficiency switching
Mode power supplies and active power factor correction.
3
Absolute maximum ratings
Symbol
Parameter
VDSS
ID
IDM
VGS
EAS
EAR
dv/dt
PD
TSTG, TJ
TL
Drain to Source Voltage
Continuous Drain Current (@TC=25oC)
Continuous Drain Current (@TC=100oC)
Drain current pulsed
(note 1)
Gate to Source Voltage
Single pulsed Avalanche Energy
(note 2)
Repetitive Avalanche Energy
(note 1)
Peak diode Recovery dv/dt
(note 3)
Total power dissipation (@TC=25oC)
Derating Factor above 25oC
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering
purpose, 1/8 from Case for 5 seconds.
*. Drain current limited by maximum junction temperature.
Thermal characteristics
Symbol
RthJC
RthCS
RthJA
Parameter
Thermal resistance, Junction to case
Thermal resistance, Case to Sink
Thermal resistance, Junction to ambient
Value
PFP4N60
PFF4N60
600
4.5 4.5*
2.6 2.6*
16
±30
262
3.9
4.5
98 33*
0.78 0.31
-55 ~ + 150
300
Unit
V
A
A
A
V
mJ
mJ
V/ns
W
W/oC
oC
oC
Value
PFP4N60
PFF4N60
1.28 3.8
0.5
62.5
Unit
oC/W
oC/W
oC/W
Copyright@ PowerGate semiconductor USA. All rights reserved.
1/8
1 page  
PFP4N60/PFF4N60
Fig. 12. Gate charge test circuit & waveform
Same type
as DUT
1mA
VGS
VDS
DUT
VGS
QGS
QG
QGD
Charge
Fig. 13. Switching time test circuit & waveform
RG
10VIN
RL
VDS
DUT
VDD
VDS 90%
VIN 10%
td(on)
10%
tr
tON
td(off)
tf
tOFF
Fig. 14. Unclamped Inductive switching test circuit & waveform
10VIN
RG
L
IAS
VDS
DUT
VDD
BVDSS
IAS
EAS =
1
2 L X IAS2 X
BVDSS
BVDSS - VDD
ID(t)
tp
VDS(t)
time
Copyright@ PowerGate semiconductor USA. All rights reserved.
5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PFP4N60.PDF ] | |
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