PDJ2116DEBG Datasheet PDF - Deutron Electronics
| Part Number | PDJ2116DEBG | |
| Description | 2G bits DDR3 SDRAM | |
| Manufacturers | Deutron Electronics | |
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DATA SHEET
2G bits DDR3 SDRAM
PDJ2108DEBG (256M words × 8 bits)
PDJ2116DEBG (128M words × 16 bits)
Specifications
• Density: 2G bits
• Organization:
⎯ 32M words × 8 bits × 8 banks (PDJ2108DEBG)
⎯ 16M words × 16 bits × 8 banks (EDJ2116DEBG)
• Package:
⎯ 78-ball FBGA (PDJ2108DEBG)
⎯ 96-ball FBGA (PDJ2116DEBG)
⎯ Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.5V ± 0.075V
• Data rate
⎯ 1600Mbps/1333Mbps (max.)
• 1KB page size (PDJ2108DEBG)
⎯ Row address: A0 to A14
⎯ Column address: A0 to A9
• 2KB page size (PDJ2116DEBG)
⎯ Row address: A0 to A13
⎯ Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
⎯ Sequential (8, 4 with BC)
⎯ Interleave (8, 4 with BC)
• /CAS Latency (CL): 6, 7, 8, 9, 10, 11
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6, RZQ/5 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
⎯ Synchronous ODT
⎯ Dynamic ODT
⎯ Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• /RESET pin for Power-up sequence and reset
function
• SRT range:
⎯ Normal/extended
• Programmable Output driver impedance control
• Seamless BL4 access with bank-grouping
Document Ver. 4.1 Deutron Electronics Corp.
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PDJ2108DEBG, PDJ2116DEBG
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations (×8 configuration) ............................................................................................................3
Pin Configurations (×16 configuration) ..........................................................................................................4
Electrical Conditions ......................................................................................................................................7
Absolute Maximum Ratings .......................................................................................................................... 7
Operating Temperature Condition ................................................................................................................ 7
Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................... 8
AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)....................... 8
VREF Tolerances ......................................................................................................................................... 9
Input Slew Rate Derating ............................................................................................................................ 10
AC and DC Logic Input Levels for Differential Signals ................................................................................ 15
AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) .................. 20
AC Overshoot/Undershoot Specification..................................................................................................... 23
Output Driver Impedance............................................................................................................................ 24
On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 27
ODT Timing Definitions............................................................................................................................... 29
IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................... 33
Electrical Specifications...............................................................................................................................46
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 46
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V) ..................................................................... 48
Standard Speed Bins .................................................................................................................................. 49
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)....................... 51
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)....................... 51
Block Diagram .............................................................................................................................................59
Pin Function.................................................................................................................................................60
Command Operation ...................................................................................................................................62
Command Truth Table ................................................................................................................................ 62
CKE Truth Table ......................................................................................................................................... 66
Simplified State Diagram .............................................................................................................................67
RESET and Initialization Procedure ............................................................................................................68
Power-Up and Initialization Sequence ........................................................................................................ 68
Reset and Initialization with Stable Power .................................................................................................. 69
Programming the Mode Register.................................................................................................................70
Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 70
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 70
DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 71
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5
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| Information | Total 70 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ PDJ2116DEBG.PDF Datasheet ] | |
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