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PDF HYMP112U64CP8-Y5 Data sheet ( Hoja de datos )
| Número de pieza | HYMP112U64CP8-Y5 | |
| Descripción | 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb ver-
sion C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm
width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Syn-
• Programmable Burst Length 4 / 8 with both
chrnous DRAMs (DDR2 SDRAMs) with 1.8V +/
sequential and interleave mode
- 0.1V Power Supply
• Auto refresh and self refresh supported
• All inputs and outputs are compatible with
SSTL_1.8 interface
• 8 Bank architecture
• Posted CAS
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball
FBGA(128Mx8), 84ball FBGA(64Mx16)
• Programmable CAS Latency 3 ,4 ,5, 6
• 133.35 x 30.00 mm form factor
• OCD (Off-Chip Driver Impedance Adjustment) • RoHS compliant
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
ORDERING INFORMATION
Part Name
HYMP164U64CP6-C4/Y5/S6/S5
HYMP164U64CR6-C4/Y5/S6/S5
HYMP112U64CP8-C4/Y5/S6/S5
HYMP112U64CR8-C4/Y5/S6/S5
HYMP112U72CP8-C4/Y5/S6/S5
HYMP125U64CP8-C4/Y5/S6/S5
HYMP125U64CR8-C4/Y5/S6/S5
HYMP125U72CP8-C4/Y5/S6/S5
Density
512MB
512MB
1GB
1GB
1GB
2GB
2GB
2GB
Org.
64Mx64
64Mx64
128Mx64
128Mx64
128Mx72
256Mx64
256Mx64
256Mx72
# of
DRAMs
4
4
8
8
9
16
16
18
# of
ranks
1
1
1
1
1
2
2
2
Materials
Lead-free
Halogen-free
Lead-free
Halogen-free
Lead-free
Lead-free
Halogen-free
Lead-free
ECC
None
None
None
None
ECC
None
None
ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6 / Jul. 2008
1
1 page  
1240pin DDR2 SDRAM Unbuffered DIMMs
PIN ASSIGNMENT(Continued)
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
23 VSS 63
A2 103 VSS 143 DQ20 183 A1 223 DM6
24 DQ16 64
VDD 104 DQS6 144 DQ21 184 VDD 224
NC
25 DQ17 65
VSS 105 DQS6 145 VSS 185 CK0 225 VSS
26 VSS 66 VSS 106 VSS 146 DM2 186 CK0 226 DQ54
27 DQS2 67 VDD 107 DQ50 147 NC 187 VDD 227 DQ55
28 DQS2 68 NC 108 DQ51 148 VSS 188 A0 228 VSS
29 VSS 69 VDD 109 VSS 149 DQ22 189 VDD 229 DQ60
30 DQ18 70 A10/AP 110 DQ56 150 DQ23 190 BA1 230 DQ61
31 DQ19 71
BA0 111 DQ57 151 VSS 191 VDDQ 231 VSS
32 VSS 72 VDDQ 112 VSS 152 DQ28 192 RAS 232 DM7
33 DQ24 73 WE 113 DQS7 153 DQ29 193 S0 233 NC
34 DQ25 74
CAS 114 DQS7 154 VSS 194 VDDQ 234 VSS
35 VSS 75 VDDQ 115 VSS 155 DM3 195 ODT0 235 DQ62
36 DQS3 76
S1 116 DQ58 156 NC 196 A13 236 DQ63
37 DQS3 77 ODT1 117 DQ59 157 VSS 197 VDD 237 VSS
38 VSS 78 VDDQ 118 VSS 158 DQ30 198 VSS 238 VDDSPD
39 DQ26 79
VSS 119 SDA 159 DQ31 199 DQ36 239 SA0
40 DQ27 80 DQ32 120 SCL 160 VSS 200 DQ37 240 SA1
*NC=No connect
Note :
1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products(DIMMs).
2. NC Pins should not be connected to anything, including bussing within the NC group.
Rev. 0.6 / Jul. 2008
5
5 Page 
1240pin DDR2 SDRAM Unbuffered DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Symbol
VDD
VDDQ
VIN, VOUT
Value
- 1.0 ~ 2.3
- 0.5 ~ 2.3
- 0.5 ~ 2.3
Unit Note
V1
V1
V1
Operation Conditions and Environmental Parameters
Parameter
DIMM Operating temperature(ambient)
Storage Temperature
Storage Humidity(without condensation)
DIMM Barometric Pressure(operating & storage)
DRAM Component Case Temperature Range
Symbol
TOPR
TSTG
HSTG
PBAR
TCASE
Rating
0 ~ +55
-50 ~ +100
5 to 95
105 to 69
0 ~+95
Units Notes
oC
oC 1
%1
K Pascal
oC
2
3
Note :
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Symbol
VDD
VDDL
VDDQ
VREF
VTT
VDDSPD
Parameter
Supply Voltage
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
EEPROM Supply Voltage
Min.
1.7
1.7
1.7
0.49*VDDQ
VREF-0.04
1.7
Rating
Typ.
1.8
1.8
1.8
0.50*VDDQ
VREF
-
Max.
1.9
1.9
1.9
0.51*VDDQ
VREF+0.04
3.6
Units Notes
V1
V 1,2
V 1,2
mV 3,4
V5
V
Note:
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track vari-
ations in VDDQ.
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
Rev. 0.6 / Jul. 2008
11
11 Page | ||
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