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Numéro de référence | M2Y2G64TU8HG5B-3C | ||
Description | Unbuffered DDR2 SDRAM DIMM | ||
Fabricant | Nanya | ||
Logo | |||
M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
240pin Unbuffered DDR2 SDRAM MODULE
Based on 128Mx8 DDR2 SDRAM G-die
Features
Performance:
PC2-5300 PC2-6400 PC2-8500
Speed Sort
-3C -AC -BD Unit
DIMM Latency*
5
5
6
f CK Clock Frequency 333 400 533 MHz
t CK Clock Cycle
3
2.5
1.875
ns
f DQ DQ Burst Frequency
667
800
1066
Mbps
•Programmable Operation:
• JEDEC Standard 240-pin Dual In-Line Memory Module
- Device Latency: 3, 4, 5, 6
• 128Mx64 and 256Mx64 DDR2 Unbuffered DIMM based on
- Burst Length: 4, 8
Elixir 128Mx8 DDR2 SDRAM G-die component
• Auto Refresh (CBR) and Self Refresh Modes
• Double Data Rate architecture; two data transfer per clock cycle
• Automatic and controlled precharge commands
• Differential bi-directional data strobe (DQS & )
• 14/10/1 Addressing (row/column/rank) – 1GB
• DQS is edge-aligned with data for reads and is center-aligned
• 14/10/2 Addressing (row/column/rank) – 2GB
with data for writes
• Serial Presence Detect
• Differential clock inputs (CK & )
• On Die Termination (ODT)
• Intended for 333MHz/400MHz applications
• OCD impedance adjustment.
• Inputs and outputs are SSTL-18 compatible
• Gold contacts
• VDD = VDDQ = 1.8V ± 0.1V
• 7.8 μs Max. Average Periodic Refresh Interval
• SDRAMs in 60-ball BGA Package
• RoHs Compliance.
Description
M2Y1G64TU88G7B and M2Y2G64TU8HG5B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM), organized as one rank 128Mx64 and two ranks 256Mx64 high-speed memory array. M2Y1G64TU88G7B
uses eight 128Mx8 DDR2 SDRAMs and M2Y2G64TU8G5B uses sixteen 128Mx8 DDR2 SDRAMs in BGA packages. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long
space-saving footprint.
The DIMM is intended for use in applications operating up to 333MHz (or 400MHz/533MHz) clock speeds and achieves high-speed data
transfer rates of up to 667Mbps (or 800Mbps/1066Mbps). Prior to any access operation, the device latency and burst / length
/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1 and BA2 using the mode register
set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 0.1
01/2010
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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Pages | Pages 14 | ||
Télécharger | [ M2Y2G64TU8HG5B-3C ] |
No | Description détaillée | Fabricant |
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