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PDF HYMP532S64CP6-E3 Data sheet ( Hoja de datos )
| Número de pieza | HYMP532S64CP6-E3 | |
| Descripción | 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb | |
| Fabricantes | Hynix | |
| Logotipo |  |
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200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver.
This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-
try standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
• All inputs and outputs are compatible with SSTL_1.8
interface
• Posted CAS
• Programmable CAS Latency 3, 4, 5, 6
• OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball(x8), 84ball(x16)
FBGA
• 67.60 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
HYMP532S64CP6-E3/C4/Y5/S5/S6
HYMP564S64CP6-E3/C4/Y5/S5/S6
HYMP512S64CP8-E3/C4/Y5/S5/S6
HYMP532S64CLP6-E3/C4/Y5/S5/S6
HYMP564S64CLP6-E3/C4/Y5/S5/S6
HYMP512S64CLP8-E3/C4/Y5/S5/S6
Density
256MB
512MB
1GB
256MB
512MB
1GB
Organization
32Mx64
64Mx64
128Mx64
32Mx64
64Mx64
128Mx64
# of
DRAMs
4
8
16
4
8
16
# of
ranks
1
2
2
1
2
2
Materials
Power
Consumption
Lead free*
Lead free
Lead free
Lead free
Lead free
Normal
Normal
Normal
Low
Low
Lead free
Low
Notes:
1. All Hynix’ DDR2 Lead-free parts are compliant to RoHS.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4 / Jul. 2007
1
1 page  
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB(32Mbx64) : HYMP532S64C(L)P6
3 Ω +/− 5%
CKE0
ODT0
/S 0
DQS0
/D Q S 0
DM0
DQS1
/D Q S 1
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ8
D Q 10
D Q 11
D Q 12
D Q 13
D Q 14
DQ15
LDQS
/U D Q S
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
/U D Q S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS2
/D Q S 2
DM2
DQS3
/D Q S 3
DM3
D Q 16
D Q 17
D Q 18
D Q 19
D Q 20
D Q 21
D Q 22
D Q 23
D Q 24
D Q 25
D Q 26
D Q 27
D Q 28
D Q 29
D Q 30
D Q 31
LDQS
/L D Q S
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
/U D Q S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 1 5
/S 1
ODT1
CKE1
/C S O D T C K E
D0
/C S O D T C K E
D1
N .C .
N .C .
N .C .
DQS4
/D Q S 4
DM4
DQS5
/D Q S 5
DM5
DQS6
/D Q S 6
DM6
DQS7
/D Q S 7
DM7
D Q 32
D Q 33
D Q 34
D Q 35
D Q 36
D Q 37
D Q 38
D Q 39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS
/L D Q S
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
/U D Q S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
/L D Q S
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
/U D Q S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/C S O D T C K E
D2
/C S O D T C K E
D3
B A 0-B A 1
A 0-A N
/R A S
/C A S
/W E
3 Ω +/- 5%
S D R A M S D 0-3
S D R A M S D 0-3
S D R A M S D 0-3
S D R A M S D 0-3
S D R A M S D 0-3
CK0
/C K 0
CK1
/C K 1
2 loads
2 lo ad s
SCL
SA0
SA1
SCL
A0
A1
A2
SDA
S e ria l P D
WP
SDA
VDD SPD
V REF
VDD
VSS
S e ria l P D
SD R A M S D O -D 3
S D R A M S D O -D 3, VD D and V D D Q
S D R A M S D O -D 3, S P D
N o te s :
1 . R e sisto r va lu e s a re 2 2 O h m + /- 5 %
Rev. 0.4 / Jul. 2007
5
5 Page 
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
VOTR
Parameter
Output Timing Measurement Reference Level
Notes:
1. The VDDQ of the device under test is referenced.
SSTl_18
0.5 * VDDQ
Units
V
Notes
1
OUTPUT DC CURRENT DRIVE
Symbol
Parameter
SSTl_18
Units
Notes
IOH(dc)
IOL(dc)
Output Minimum Source DC Current
Output Minimum Sink DC Current
- 13.4
13.4
mA 1, 3, 4
mA 2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 0.4 / Jul. 2007
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet HYMP532S64CP6-E3.PDF ] | |
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