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M2S2G64CB88B5N fiches techniques PDF

Nanya - Unbuffered DDR3 SO-DIMM

Numéro de référence M2S2G64CB88B5N
Description Unbuffered DDR3 SO-DIMM
Fabricant Nanya 
Logo Nanya 





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M2S2G64CB88B5N fiche technique
M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Based on DDR3-1066/1333/1600 128Mx16 (1GB) / 256Mx8 (2GB) / 256Mx8 (4GB) SDRAM B-Die
Features
•Performance:
Speed Sort
PC3-8500 PC3-10600 PC3-12800
-BE -CG
-DI Unit
DIMM CAS Latency
7 9 11
fck Clock Frequency
533 667
800
tck Clock Cycle
1.875
1.5
1.25
fDQ DQ Burst Frequency 1066
1333
1600
204-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
1GB: 128Mx64 Unbuffered DDR3 SO-DIMM based on 128Mx16
MHz
ns
Mbps
Programmable Operation:
- DIMM  Latency: 5, 6, 7, 8/PC3-8500; 5, 6, 7, 8,
DDR3 SDRAM B-Die devices.
2GB: 256Mx64 Unbuffered DDR3 SO-DIMM based on 256Mx8
9/PC3-10600; 5, 6, 7, 8, 9, 10, 11/PC3-12800
- Burst Type: Sequential or Interleave
DDR3 SDRAM B-Die devices.
4GB: 512Mx64 Unbuffered DDR3 SO-DIMM based on 256Mx8
DDR3 SDRAM B-Die devices.
Intended for 533MHz/667MHz/800MHz applications
• Inputs and outputs are SSTL-15 compatible
VDD = VDDQ = 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
DRAM DLL aligns DQ and DQS transitions with clock transitions.
Address and control signals are fully synchronous to positive
clock edge
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
Two different termination values (Rtt_Nom & Rtt_WR)
14/10/1 (row/column/rank) Addressing for 1GB
15/10/1 (row/column/rank) Addressing for 2GB
15/10/2 (row/column/rank) Addressing for 4GB
Extended operating temperature rage
Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
1GB: SDRAMs are in 96-ball BGA Package
2GB: SDRAMs are in 78-ball BGA Package
4GB: SDRAMs are in 78-ball BGA Package
RoHS compliance and Halogen free
Description
M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N are un-buffered 204-Pin Double Data Rate 3 (DDR3) Synchronous
DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 128Mx64 (1GB) and one rank of 256Mx64 (2GB)
/ 512Mx64 (4GB) high-speed memory array. Modules use four 128Mx16 (1GB) 96-ball BGA packaged devices and eight 256Mx8 (2GB)
78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw
cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All Elixir DDR3 SODIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz/800MHz clock speeds and achieves high-speed data transfer
rates of 1066Mbps/1333Mbps/1600Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be
programmed into the DIMM by address inputs A0-A13 (1GB)/A0-A14 (2GB/4GB) and I/O inputs BA0~BA2 using the mode register set
cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
09/2010
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

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