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PDF H27UCG8T2ATR-BC Data sheet ( Hoja de datos )
| Número de pieza | H27UCG8T2ATR-BC | |
| Descripción | 64Gb(8192M x 8bit) Legacy MLC NAND Flash | |
| Fabricantes | Hynix | |
| Logotipo |  |
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H27UCG8T2ATR-BC Series
64Gb(8192M x 8bit) Legacy MLC NAND Flash
F20 64Gb MLC
NAND Flash Memory
TSOP Legacy
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 1.1/ Nov. 2011
1
1 page  
H27UCG8T2ATR-BC Series
64Gb(8192M x 8bit) Legacy MLC NAND Flash
3.18. Random Data Input Timings ………………………………………………………………………………… 33
3.19. Multi Plane Page Program Operation Timings ………………………………………………………….. 34
3.20.
3.21.
Copy-Back Program Operation Timings with Random Date Input .………………………………..
Cache Program Operation Timings …………………………………………………………………………
35
35
3.22. Multi Plane Cache Program Operation Timings …………………………………………………………. 36
3.23. Block Erase Operation Timings ……………………………………………………………………………… 36
3.24. Multi Plane Erase Operation Timings ...................................................................................... 37
3.25. Reset Timings …………………………………………………………………………………………………… 37
4. Device Operation …………………………………………………………………………………………………… 38
4.1. Page Read ………………………………………………………………………………………………………….. 38
4.2. Cache Read ………………………………………………………………………………………………………… 39
4.3. Cache Read Enhanced ………………………………………………………………………………………….. 39
4.4. Multi Plane Page Read ………………………………………………………………………………………….. 40
4.5. Multi Plane Cache Read ………………………………………………………………………………………... 41
4.6. Multi Plane Cache Read Enhanced ………………………………………………………………………….. 41
4.7. Read ID …………………………………………………………………………………………………………….. 42
4.8. Read Status Register ……………………………………………………………………………………………. 42
4.9. Page Program …………………………………………………………………………………………………….. 43
4.10. Multi Plane Program …………………………………………………………………………………………… 44
4.11. Cache Program .…………………………………………………………………………………………………. 45
4.12. Multi Plane Cache Program .…………………………………………………………………………………. 47
4.13. Copy-Back Program ……………………………………………………………………………………………. 48
4.14. Multi-Plane Copy-Back Program ……………………………………………………………………………. 49
4.15. Block Erase ……………………………………………………………………………………………………….. 50
4.16. Multi Plane Block Erase ……………………………………………………………………………………….. 51
4.17. Reset ………………………………………………………………………………………………………………. 51
5. Other Features ………………………………………………………………………………………………………. 52
5.1. Data Protection & Power on/off Sequence ………………………………………………………………… 52
5.2. Ready / Busy .……………………………………………………………………………………………………… 53
5.3. Write Protect Operation ………………………………………………………………………………………… 54
6. Application notes and comments……………………………………………………………………………… 55
6.1. Paired Page Address Information…………………………………………………………………………….. 56
Rev 1.1/ Nov. 2011
5
5 Page 
H27UCG8T2ATR-BC Series
64Gb(8192M x 8bit) Legacy MLC NAND Flash
1.7. Addressing
Bus cycle
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st Cycle
2nd Cycle
3rd Cycle
A0 A1 A2 A3 A4 A5 A6 A7
A8 A9 A10 A11 A12 A13 L(1) L(1)
A14 A15 A16 A17 A18 A19 A20 A21
4th Cycle
A22 A23 A24 A25 A26 A27 A28 A29
5th Cycle
A30 A31 A32 A33 A34 L(1) L(1) L(1)
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22),
and block address (A23 ~ the last address).
1.8. Extended Blocks Arrangement
The device offers 84 extended blocks to increase valid blocks. These blocks can be accessed when the block
address A34 is ‘High’.
Row Address
(Hexadecimal)
000000h
000100h
000200h
000300h
000400h
000500h
·
·
·
0FFD00h
0FFE00h
0FFF00h
100000h
100100h
·
·
·
104E00h
104F00h
104FFFh
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
·
·
·
Block 4093
Block 4094
Block 4095
Block 4096
Block 4097
·
·
·
Block 4178
Block 4179
Main Blocks
(4096 Blocks)
Extended Blocks
(84 Blocks)
Rev 1.1/ Nov. 2011
11
11 Page | ||
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| PDF Descargar | [ Datasheet H27UCG8T2ATR-BC.PDF ] | |
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