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PDF RT9232 Data sheet ( Hoja de datos )
| Número de pieza | RT9232 | |
| Descripción | Programmable Frequency Synchronous Buck PWM Controller | |
| Fabricantes | Richtek | |
| Logotipo |  |
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RT9232
Programmable Frequency Synchronous Buck PWM Controller
General Description
The RT9232 is a single-phase synchronous buck PWM
DC-DC converter controller designed to drive twoN-Channel
MOSFET. It provides a highly accurate, programmable
output voltage precisely regulated to low voltage
requirement with an internal 0.8V ± 1% reference.
The RT9232 uses an external compensated, single
feedback loop voltage mode PWM control for fast transient
response. An oscillator with Programmable frequency
(50kHz to 800kHz) reduces the external inductor and
capacitor component size for saving PCB board area.
The RT9232 provides fast transient response to satisfy
high current output applications (up to 25A) while
minimizing external components. It is suitable for high-
performance graphic processors, DDR and VTT power.
The RT9232 integrates complete protect functions such
as Soft Start, Output Enable, UVLO(under-voltage lockout)
into a small 14-pin package.
Ordering Information
RT9232
Package Type
S : SOP-14
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100%matte tin (Sn) plating.
DS9232-06 March 2007
Features
Single IC Supply Voltage: 12V
Single phase DC/DC Buck Converter with
`High Output Current (up to 25A )
`Low Output Voltage (down to 0.8V )
`High Input Voltage (up to 12V )
Operate from 12V, 5V or 3.3V Input
0.8V ± 1% Internal Reference
Adaptive Non-Overlapping Gate Drivers
Integrated High-Current, HV Gate Drivers
External Programmable Soft Start
External Programmable Frequency
(Range: 50kHz to 800kHz, 200kHz Free Run )
Integrated Output Short Circuit Protection
On/Off Control by Enable Pin
Drives Two N-Channel MOSFET
Full 0 to 100% Duty Cycle
Fast Transient Response
Voltage Mode PWM Control with External
Feedback Loop Compensation
RoHS Compliant and 100% Lead (Pb)-Free
Applications
System (Graphic, MB) with 12V Power.
Graphic Cards (AGP 8X, 4X, PCI Express*16):
`High-Current for High-Performance Graphic Processors
(GPU, VPU)
`Middle Current for High-Performance Graphic Memory
Power (DDR, DDR II)
`Low Current with Sink Capacity for High-Performance
Graphic Memory Power (DDR/VTT)
3.3V to 12V Input DC-DC Regulators
Low Voltage Distributed Power Supplies
Pin Configurations
(TOP VIEW)
RT
SENSE
SS
COMP
FB
EN
GND
2
3
4
5
6
7
14 VCC
13 PVCC
12 LGATE
11 PGND
10 BOOT
9 UGATE
8 PHASE
SOP-14
www.richtek.com
1
1 page  
RT9232
Parameter
Symbol
Test Conditions
Min Typ Max Units
Error Amplifier
DC gain
-- 88 -- dB
Gain-Bandwidth product
GBW
-- 15 -- MHz
Slew Rate
SR COMP = 10pF
-- 6 -- V/μs
Soft Start
External SS Source Current
ISS
7 10 -- μA
PWM Controller Gate Driver
Upper Drive Source
Upper Drive Sink
Lower Drive Source
Lower Drive Sink
RUG_SC
RUG_SK
RLG_SC
RLG_SK
VBOOT – PHASE = 12V
VBOOT – UGATE = 1V
VBOOT – PHASE = 12V
VUGATE – PHASE = 1V
VPVCC – LGATE = 1V
VLGATE – PGND = 1V
-- 9 12 Ω
-- 5 8
-- 2.5 4
-- 2.5 4
Ω
Ω
Ω
Driving Capability
Upper Drive Source
Upper Drive Sink
Lower Drive Source
Lower Drive Sink
IUG_SC
IUG_SK
ILG_SC
ILG_SK
VBOOT – UGATE = 12V
VUGATE – PHASE = 12V
VPVCC – LGATE = 12V
VLGATE – PGND = 12V
-- 1 --
-- 1 --
-- 2.4 --
-- 2 --
A
A
A
A
Protection
Under-Voltage Protection
Under-Voltage Protection Delay
FB Falling
0.5 0.6 0.7
-- 30 --
V
μs
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
DS9232-06 March 2007
www.richtek.com
5
5 Page 
RT9232
ΔIL
=
(VIN −
VOUT) x
VOUT
VIN x fOSC x L
(5)
Generally, an inductor that limits the ripple current between
20% and 50% of output current is appropriate. Make sure
that the output inductor could handle the maximum output
current and would not saturate over the operation
temperature range.
Output Capacitor Selection
The output capacitors determine the output ripple voltage
(ΔVOUT) and the initial voltage drop after a high slew-rate
load transient. The selection of output capacitor depends
on the output ripple requirement. The output ripple voltage
is described as Equation (6).
ΔVOUT
=
ΔIL
x
ESR +
1
8
x
fO2SC
VOUT
x L x COUT
(1− D)
(6)
For electrolytic capacitor application, typically 90~95%
of the output voltage ripple is contributed by the ESR of
output capacitors. Paralleling lower ESR ceramic capacitor
with the bulk capacitors could dramatically reduce the
equivalent ESR and consequently the ripple voltage.
Input Capacitor Selection
Use mixed types of input bypass capacitors to control
the input voltage ripple and switching voltage spike across
the MOSFETs. The buck converter draws pulsewise
current from the input capacitor during the on time of upper
MOSFET. The RMS value of ripple current flowing through
the input capacitor is described as:
IIN(RMS) = IOUT x D x (1− D)
(7)
The input bulk capacitor must be cable of handling this
ripple current. Sometime, for higher efficiency the low ESR
capacitor is necessarily. Appropriate high frequency
ceramic capacitors physically near the MOSFETs
effectively reduce the switching voltage spikes.
MOSFET Selection
The selection of MOSFETs is based upon the
considerations of RDS(ON), gate driving requirements, and
thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as:
PUPPER = PCOND _UPPER + PSW_UPPER
(8)
= IOUT
x RDS(ON)
xD+
1
2
IOUT
x
VIN
x (TRISE
+ TFALL ) x
fOSC
where TRISE and TFALL are rising and falling time of VDS of
upper MOSFET respectively. RDS(ON) and QG should be
simultaneously considered to minimize power loss of upper
MOSFET.
The power loss of lower MOSFET consists of conduction
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is express as:
PLOWER = PCOND _LOWER + PRR + PDIODE
(9)
= IOUT x RDS(ON) x (1− D) + QRR x VIN x fOSC
+
1
2
x IOUT
x
VF
x
TDIODE
x
fOSC
where TDIODE is the conducting time of lower body diode.
Special control scheme is adopted to minimize body diode
conducting time. As a result, the RDS(ON) loss dominates
the power loss of lower MOSFET. Use MOSFET with
adequate RDS(ON) to minimize power loss and satisfy
thermal requirements.
Feedback Compensation
Figure 4 highlights the voltage-mode control loop for a
synchronous buck converter. Figure 5 shows the
corresponding Bode plot. The output voltage (VOUT) is
regulated to the reference voltage. The error amplifier EA
output (COMP) is compared with the oscillator (OSC)
sawtooth wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (L and COUT).
The modulator transfer function is the small-signal transfer
function of VOUT/COMP. This function is dominated by a
DC gain and the output filter (L and COUT), with a double
pole break frequency at FP_LC and a zero at FZ_ESR. The
DC gain of the modulator is simply the input voltage (VIN)
divided by the peak-to-peak oscillator voltage ΔVOSC.
The break frequency FLC and FESR are expressed as
Equation (10) and (11) respectively.
FP_LC = 2π
1
LCOUT
(10)
FZ_ESR
=
2π
1
x ESR
x COUT
(11)
DS9232-06 March 2007
www.richtek.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet RT9232.PDF ] | |
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