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PDF DS856 Data sheet ( Hoja de datos )
| Número de pieza | DS856 | |
| Descripción | High Speed 3GHz Direct Digital Synthesizer | |
| Fabricantes | Euvis | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS856 (archivo pdf) en la parte inferior de esta página. Total 39 Páginas | ||
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Euvis
DS856 Datasheet
Document name: DS856_DS_Ver01
Release date: 7/17/2008
Related document:
Version: DS856
Revision: V01
1. Add more spectrum data
1 page  
Euvis
High-Speed Direct Digital Frequency Synthesizer, DS856
Theory of Operation
The DS856 core consists of a 32-bit accumulator, a sine wave look up table in the form
of a ROM, and a 11-bit Digital to Analog Converter (DAC). The 32-bit accumulator is a
phase accumulator, where the 32 frequency control bits are latched and added to the
previous output of the accumulator at each clock cycle. The accumulator output stores
the phase of the output waveform of the chip. Sine wave generation requires the phase
from the accumulator be passed to a ROM to look up the appropriate amplitude for the
waveform. To save on size the ROM only stores the first quadrant of sine wave data. To
form the full pattern the two most significant bits of the phase are used with the first
quadrant data to generate the full sine wave. The final 11-bit digital outputs of the ROM
are passed to the DAC stage to synthesize the sine waveform. The DAC employs R-2R
ladders and segmented architecture to improve linearity and reduce output glitches. The
22 current switches are all differential to produce a complementary pair of output signals.
All 11 data bits of the digital outputs of the ROM are re-latched with the same
clock edge, providing a uniform setup time for the DAC stage. Then the 4 MSB bits are
decoded into fifteen lines. The decoding employed reduces output glitches and improves
dc linearity. The remaining 7 LSB bits (D0-D6) are passed on unchanged. The clock
latches all 22 lines again. The latched data controls 7 R-2R and 15 segmented current
switches respectively to produce the analog outputs. The four MSB bits control 15
identical current switches, while the seven LSB bits control 7 current switches connected
through an R-2R ladder. The output signals should be connected with 50-Ω terminations
to ground. Once terminated each output will produce a 600 mV full-scale voltage range.
The differential outputs can be combined with a broadband balun to achieve 1.2V single
ended output with the even-order harmonics suppressed to certain degree.
The state of the accumulator can be reset to zero when RST is set to voltage
higher than 1.0V. This has the effect of setting the initial phase of the sine wave to zero.
In normal operation RST should be set at 0V. When the accumulator overflows, a carry
output bit is propagated to COUT. COUT has a 250-Ω back termination with 4 mA
current sink. The COUT signal can be very useful to trigger or synchronize the DDS
outputs with other chips, functions or equipments in the system. A pair of
complementary clock inputs with 50-Ω terminations to VTT are provided. VTT acts as
the logic threshold and can be set by the user. Once the 32 parallel frequency control
data input bits Vi[0:31] are settled at the input pins, the high speed strobe pulse
(STRP/STRN) will latch (at the negative transition edge) the 32 data input bits into
accumulator and initiate new frequency signal at the DAC outputs. The phase of output
signals will be continuous between the two output frequency signals before and after the
strobe pulse. This high speed strobe feature allows DS856 to be controlled by micro-
controller or DSP chips for real time chirping function.
Ver. 01, 7/17/08
5
5 Page 
Euvis
High-Speed Direct Digital Frequency Synthesizer, DS856
BIT WEIGHT OF FREQUENCY WORD INPUTS
BIT POSISTION
Vi0 (LSB)
Vi1
Vi2
Vi3
Vi4
Vi5
Vi6
Vi7
Vi8
Vi9
Vi10
Vi11
Vi12
Vi13
Vi14
Vi15
Vi16
Vi17
Vi18
Vi19
Vi20
Vi21
Vi22
Vi23
Vi24
Vi25
Vi26
Vi27
Vi28
Vi29
Vi30
Vi31(MSB)
FREQUENCY PER BIT POSISTION
F(CLK)/2^32
F(CLK)/2^31
F(CLK)/2^30
F(CLK)/2^29
F(CLK)/2^28
F(CLK)/2^27
F(CLK)/2^26
F(CLK)/2^25
F(CLK)/2^24
F(CLK)/2^23
F(CLK)/2^22
F(CLK)/2^21
F(CLK)/2^20
F(CLK)/2^19
F(CLK)/2^18
F(CLK)/2^17
F(CLK)/2^16
F(CLK)/2^15
F(CLK)/2^14
F(CLK)/2^13
F(CLK)/2^12
F(CLK)/2^11
F(CLK)/2^10
F(CLK)/2^9
F(CLK)/2^8
F(CLK)/2^7
F(CLK)/2^6
F(CLK)/2^5
F(CLK)/2^4
F(CLK)/2^3
F(CLK)/2^2
F(CLK)/2
Ver. 01, 7/17/08
11
11 Page | ||
| Páginas | Total 39 Páginas | |
| PDF Descargar | [ Datasheet DS856.PDF ] | |
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