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PDF AND9131 Data sheet ( Hoja de datos )
| Número de pieza | AND9131 | |
| Descripción | Designing a LED Driver | |
| Fabricantes | ON Semiconductor | |
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AND9131/D
Designing a LED Driver with
the NCL30080/81/82/83
Introduction
As LED lighting finds its way into low wattage
applications, lamp designers are challenged for a variety of
conflicting requirements. Size is often dictated by the
incumbent lamp and fixture size whether it’s A19, GU10,
etc. Thermal performance, reliability, safety, and EMC
requirements also present design challenges. The
NCL3008X family of controllers incorporates all the
features and protection needed to design compact low
wattage LED drivers with a minimum of external
components.
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APPLICATION NOTE
Overview
The NCL3008X is a family of 4 controllers in 2 different
packages (Micro 8 and TSOP6). The 8 pin packaged parts
have 2 extra pins for Dimming and thermal / over voltage
protection. The 6 pin package parts have all the basic control
and protection feature required to make a low parts count
LED driver.
Table 1. PRODUCT MATRIX
Product
NCL30080A/B
NCL30081A/B
NCL30082A/B
NCL30083A/B
Package
TSOP6
TSOP6
Micro-8
Micro-8
Thermal Foldback
No
No
Yes
Yes
Analog/Digital Dimming
No
No
Yes
Soft-start
5 Step LOG Dimming
No
Yes
No
Yes
In the A versions of the NCL3008X, some protections are
latched. In the B versions, all faults are auto-recoverable.
The controllers have a built in control algorithm that
allows to precisely regulate the output current of a Flyback
converter from the primary side. This eliminates the need for
an optocoupler and associated circuitry. The control scheme
also support Buck-boost and SEPIC topology. The output
current regulation is within ± 2% over a line range of
85-265 V rms.
The power control uses a Critical Conduction Mode
(CrM) approach with valley switching to optimize
efficiency and EMI filtering. The controller selects the
appropriate valley for operation which keeps the frequency
within a tighter range than would normally be possible with
simple CrM operation.
Constant Current Control
In a Flyback converter, the leakages inductances slow
down the primary current decay and the secondary current
rise. Thus, the current transfer from primary to secondary
side is delayed and the secondary peak current is reduced:
ID,pk
t
IL,pk
Nsp
(eq. 1)
The diode current reaches its peak when the leakage
inductor is reset. Thus, in order to accurately regulate the
output current, the leakage inductor current must be taken
into account. This is accomplished by sensing the clamping
network current. Practically, a node of the clamp capacitor
is connected to Rsense instead of the bulk voltage Vbulk.
Then, by reading the voltage on the CS pin, we have an
image of the primary current (red curve in Figure 3).
When the diode conducts, the secondary current decreases
linearly from ID,pk to zero. When the diode current has
turned off, the drain voltage begins to oscillate because of
the resonating network formed by the inductors (Lp+Lleak)
and the lump capacitor. This voltage is reflected on the
auxiliary winding wired in fly-back mode. Thus, by looking
at the auxiliary winding voltage, we can detect the end of the
conduction time of secondary diode. The constant current
control block picks up the leakage inductor current, the end
of conduction of the output rectifier and controls the drain
current to maintain the output current Iout constant. We have:
Iout
+
VREF
2NspRsense
(eq. 2)
The output current value is set by choosing the sense
resistor:
Rsense
+
Vref
2NspIout
(eq. 3)
© Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. 0
1
Publication Order Number:
AND9131/D
1 page  
AND9131/D
ǒ Ǔ ǒ ǓRZCD w max
Vaux(high)
IZCD(max))
,
Vaux(low)
IZCD(max*)
+ max
28.5
5m
,
*63.7
*2m
+ max (5.7k, 31.8k) + 31.8 kW
(eq. 9)
Then, we can use this Bx value to approximate the
resistance at 25°C of the thermistor needed:
ǒ ǓR25 +
RTFstart
eBx
11
TTFstart 25)273
(eq. 12)
Selecting the NTC
There are different ways to select the thermistor
depending on the critical parameter for the designer. We will
consider the temperature TTFstart at which the thermal
foldback starts and the temperature TOTP at which the over
temperature protection (OTP) must triggers as our design
parameters.
The controller starts to reduce the output current when the
voltage on SD pin drops below 1 V which correspond to a
resistance between SD pin and ground: RSD ≤ 11.76 kW. The
current reduction is stopped when RSD ≤ 8 kW: the output
current is clamped to 50 % of its nominal value. The
controllers detects an over temperature and shuts down
when RSD ≤ 5.88 kW.
As a starting point, we can try to calculate the sensitivity
index or constant B of the material needed to meet our
temperature requirements. The formula for B can be found
in the thermistor manufacturers’ application notes or
datasheets. To calculate the B value, it is necessary to know
the resistances R1 and R2 of the thermistor at the
temperatures T1 and T2.
ǒ ǓB
+
T1T2
T2*T1
ln
R1
R2
(eq. 10)
In our case, this equation can be translated as follows:
ǒ ǓBx
+
TOTPTTFstart
TOTP*TTFstart
ln
RTFstart
ROTP
(eq. 11)
Where:
TTFstart is the temperature at which the thermal foldback
should start
RTFstart is the corresponding resistance mentioned above:
RTFstart = 11.76 kW
TOTP is the temperature at which the OTP must trigger
ROTP is the corresponding resistance mentioned above:
ROTP = 5.88 kW
Generally, the B given by the manufacturer is calculated
for 25°C and 85°C. The value of B depends on the
temperatures by which it is calculated. That’s why in our
case it is an approximate value and we might consider
looking for a material within ± 5% of the calculated Bx.
Design example:
TTFstart = 75°C = 348 K
TOTP = 95°C = 368 K
ǒ Ǔ ǒ ǓBx
+
TOTPTTFstart
TOTP*TTFstart
ln
RTFstart
ROTP
+
348 368
368*348
ln
11.76k
5.88k
+
+ 4438 K
(eq. 13)
ǒ Ǔ ǒ ǓR25 +
RTFstart
eBx
11
TTFstart 25)273
+
11.76k
e4438
11
348 298
+ 99.9 kW
(eq. 14)
Finally, we select a NTC with B25/85 = 4220 and R25 =
100 kW.
From the manufacturer tables of resistance vs temperature
R(T), we have the following values:
R75 = 13.16 kW, R80 = 11.06 kW meaning the temperature
foldback point is between 75°C and 80°C.
R95 = 6.74 kW, R100 = 5.76 kW meaning the OTP trip
point is between 95°C and 100°C.
It is also possible to place a resistor in parallel of the NTC
to modify its R(T) characteristic.
Selecting the SD Pin Capacitor
The SD pin capacitor must not exceed 4.7 nF so that the
controller is able to start in every conditions, in particular
when RSD is around 8 kW.
Indeed at startup, the controller waits for 180 ms minimum
before starting the DRV pulses in order to allow the current
source to charge CSD. If a too big capacitor is used, the SD
pin voltage will not be able to increase above 0.5 V before
the 180 ms timer ends. Thus, the controller will detect an over
temperature condition.
Designing the CS Pin Network (RLFF, CCS)
The propagation delay tprop from the current-sense
voltage reaching the programmed internal threshold Vcontrol
to the MOSFET off-state influences the output current
regulation and must be taken into account. The peak current
increase caused by tprop must be compensated.
IL
Vcontrol
Rsense
DIL,pkH
DIL,pkL
High
Line
Low
Line
tprop tprop time
Figure 8. Propagation Delay Effect on Peak Current
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5
5 Page 
Choosing the MOSFET breakdown voltage
BVdss
Vds,max
Vos
AND9131/D
15% derating
Vreflect
Vbulk,max
Vclamp
Figure 13. MOSFET Drain−source Voltage at High Line
Figure 13 shows the waveform of the drain-source voltage
of a MOSFET operated in the 1st valley.
We can estimate the maximum voltage reached on the
drain node, considering Vout(OVP) level as the maximum
output voltage:
Vds,max
+
Vin,max
Ǹ2
)
(Vout(OVP) )
Nsp
Vf)
kc
)
Vos
(eq. 44)
Where:
kc is the clamping coefficient (kc = Vclamp / Vreflect) [1].
kc should be keep in the range of 1.3 to 1.5 times the reflected
voltage.
Vos is the drain voltage overshoot caused by the clamping
diode recovery time.
After calculating the maximum drain-source voltage, we
apply a safety factor of 15% in order to select the breakdown
voltage of the MOSFET, meaning that:
BVdss
w
Vds,max
(1*0.15)
(eq. 45)
The following table gives the maximum drain-source
voltage considering a 15% derating factor for MOSFET
breakdown voltage found on the market.
Table 3. Vds,max AFTER 15% DERATING HAS BEEN
APPLIED TO BVdss
Breakdown Voltage
(BVdss)
Maximum drain-source
voltage (Vds,max)
500 V
425 V
600 V
510 V
650 V
553 V
800 V
680 V
Using (eq.44), we calculate the MOSFET Vds,max in our
design:
Vds,max
+
Vin,max
Ǹ2
)
(Vout(OVP) )
Nsp
Vf)
kc
)
Vos
+
+
265
Ǹ2
)
(28 ) 0.6)
0.167
1.6
)
20
+
668
V
(eq. 46)
Looking at Table 3, we select an 800 V MOSFET.
Choosing the MOSFET RDSon
Space is very limited in a LED bulb, and there is no space
to add a heatsink for the power MOSET or the output
rectifier. Thus, the MOSFET will be chosen such that it can
dissipate the power in all conditions without using a
heatsink.
Knowing the chosen package thermal resistance RqJA, we
first calculate the power that can be dissipated by this
package at a chosen maximum ambient temperature
TA(MAX).
Ppack
+
TJ(MAX)*TA(MAX)
RqJA
(eq. 47)
In a quasi-square wave resonant power supply operating
at low line and full load, the MOSFET losses are mainly
conduction losses. The MOSFET RDSon at TJ(MAX) can be
estimated:
RDSonǒTJǓ
+
Ppack
Ipri,rms2
(eq. 48)
In equation (48), Ipri,rms is the rms current in the primary
side of the flyback transformer at lowest input voltage and
full output load:
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11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AND9131.PDF ] | |
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