IDT74FCT824B Datasheet PDF - Integrated Device Technology
| Part Number | IDT74FCT824B | |
| Description | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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®
Integrated Device Technology, Inc.
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
FEATURES:
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FAST™ speed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) – ideal for parity bus interfacing in high-perform-
ance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT821/823/825
D0 DN
EN
IDT54/74FCT824
D0
EN
DN
CLR
CP
D CL Q
CP Q
D CL Q
CP Q
CLR
CP
OE
Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
YN
2608 cnv* 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.19
OE
D CL Q
CP Q
D CL Q
CP Q
Y0 YN
2608 cnv* 02
MAY 1992
DSC-4618/2
1
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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max. Unit
ICC
Quiescent Power Supply Current VCC = Max.
VIN ≥ VHC; V IN ≤ VLC
— 0.2 1.5 mA
∆ICC
Quiescent Power Supply Current VCC = Max.
TTL Inputs HIGH
VIN = 3.4V(3)
— 0.5 2.0 mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN ≥ VHC
VIN ≤ VLC
— 0.15 0.25 mA/
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN ≥ VHC
— 1.7 4.0 mA
Outputs Open
VIN ≤ VLC
fCP = 10MHz
(FCT)
50% Duty Cycle
OE = EN = GND
VIN = 3.4V
— 2.2 6.0
One Bit Toggling
VIN = GND
at f i = 5MHz
50% Duty Cycle
VCC = Max.
VIN ≥ VHC
— 4.0 7.8(5)
Outputs Open
VIN ≤ VLC
fCP = 10MHz
(FCT)
50% Duty Cycle
OE = EN = GND
VIN = 3.4V
— 6.2 16.8(5)
Eight Bits Toggling
VIN = GND
at f i = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
2608 tbl 07
7.19 5
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