M392B5170FM0 Datasheet PDF - Samsung
| Part Number | M392B5170FM0 | |
| Description | 240pin VLP Registered DIMM | |
| Manufacturers | Samsung | |
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There is a preview and M392B5170FM0 download ( pdf file ) link at the bottom of this page. Total 41 Pages | ||
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Rev. 1.01, Dec. 2010
M392B2873FH0
M392B5673FH0
M392B5670FH0
M392B5170FM0
240pin VLP Registered DIMM
based on 1Gb F-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
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VLP Registered DIMM
datasheet
Rev. 1.01
DDR3 SDRAM
1. DDR3 VLP Registered DIMM Ordering Information
Part Number2
Density
Organization
M392B2873FH0-CF8/H9
M392B5673FH0-CF8/H9
M392B5670FH0-CF8/H9
M392B5170FM0-CF8/H9
1GB
2GB
2GB
4GB
128Mx72
256Mx72
256Mx72
512Mx72
NOTE :
1. "##" - F8/H9
2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
Component Composition
128Mx8(K4B1G0846F-HC##)*9
128Mx8(K4B1G0846F-HC##)*18
256Mx4(K4B1G0446F-HC##)*18
DDP 512Mx4(K4B2G0446F-MC##)*18
Number of
Rank
1
2
1
2
Height
18.75mm
18.75mm
18.75mm
18.75mm
2. Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066) and 7(DDR3-1333)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
3. Address Configuration
Organization
256Mx4(1Gb) based Module
128Mx8(1Gb) based Module
512Mx4(2Gb DDP) based Module
Row Address
A0-A13
A0-A13
A0-A13
Column Address
A0-A9, A11
A0-A9
A0-A9, A11
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
A10/AP
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| Information | Total 41 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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