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PDF CPC7592BA Data sheet ( Hoja de datos )
| Número de pieza | CPC7592BA | |
| Descripción | Line Card Access Switch | |
| Fabricantes | IXYS | |
| Logotipo |  |
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INTEGRATED CIRCUITS DIVISION
CPC7592
Line Card Access Switch
Features
• TTL logic level inputs for 3.3V logic interfaces
• Smart logic for power up / hot plug state control
• Monolithic IC reliability
• Low matched RON
• Eliminates the need for zero cross switching
• Flexible switch timing to transition from ringing mode
to talk mode.
• Clean, bounce-free switching
• Tertiary protection consisting of integrated current
limiting, voltage clamping, and thermal shutdown for
SLIC protection
• 5V operation with power consumption < 10 mW
• Intelligent battery monitor
• Latched logic-level inputs, no external drive circuitry
required
• Small 16-pin SOIC Package
Applications
• VoIP Gateways
• Central office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber in the Loop (FITL)
• Pair Gain System
• Channel Banks
Pb e3
Description
The CPC7592 is a member of IXYS Integrated
Circuits Division’s next generation Line Card Access
Switch family. This monolithic 6-pole solid-state switch
is available in a 16-pin SOIC package. It provides the
necessary functions to replace two 2-Form-C
electro-mechanical relays used on traditional analog
and contemporary integrated voice and data (IVD) line
cards found in Central Office, Access, and PBX
equipment. Because this device contains solid state
switches for tip and ring line break, ringing
injection/return, and test access, it needs only a +5V
supply for operation and logic-level inputs for control.
The CPC7592 is very similar to the CPC7582 with the
addition of controlled start-up states and TTL
compatible logic inputs.
The CPC7592BC logic provides alternative test states
from the CPC7592BA/BB while also providing greater
protection SCR trigger and hold current ratings.
Ordering Information
Part #
Description
CPC7592BA
CPC7592BATR
CPC7592BB
CPC7592BBTR
CPC7592BC
CPC7592BCTR
16-Pin SOIC, with Protection SCR, 50/Tube
16-Pin SOIC, with Protection SCR, 1000/Reel
16-Pin SOIC, without Protection SCR, 50/Tube
16-Pin SOIC, without Protection SCR, 1000/Reel
16-Pin SOIC, With Protection SCR and “Monitor Test
State”, 50/Tube
16-Pin SOIC, With Protection SCR and “Monitor Test
State”, 1000/Reel
Figure 1. CPC7592 Block Diagram
TTEST
5
4 TRINGING
Tip
Ring
T 3LINE
Secondary
Protection
RLINE 14
XSW5 XSW3
X
SW1
SW2
X
XSW6 XSW4
CPC7592
+5VDC
6 VDD
2 TBAT
Switch
VREF Control
Logic
SLIC
15 RBAT
L9
A 10
T
C 11
H
INTEST
INRINGING
LATCH
RTEST
12
VBAT
13 RRINGING
1 SCR Trip Circuit
FGND (CPC7592BA/BC)
16
VBAT
87
DGND
300Ω
(min.)
RINGING
TSD
DS-CPC7592-R04
www.ixysic.com
1
1 page  
INTEGRATED CIRCUITS DIVISION
CPC7592
1.6.2 Ringing Return Switch, SW3
Parameter
Off-State
Leakage Current
On Resistance
DC current limit
Dynamic current limit
(t = <0.5 s)
Logic input to switch
output isolation
dV/dt sensitivity
Test Conditions
VSW3 (differential) = TLINE to TRINGING
All-Off state.
+25 C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85 C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
-40 C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
ISW(on) = ±0 mA, ±10 mA, +25 C
ISW(on) = ±0 mA, ±10 mA, +85 C
ISW(on) = ±0 mA, ±10 mA, -40 C
VSW (on) = ± 10 V, +25 C
VSW (on) = ± 10 V, +85 C
VSW (on) = ± 10 V, -40 C
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 s pulse with
appropriate protection in place.
+25 C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±320 V
+85 C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±330 V
-40 C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±310 V
-
Symbol
ISW
RON
ISW
ISW
ISW
-
Minimum
-
-
-
70
-
-
-
-
Typical
0.1
0.3
0.1
60
85
45
135
85
210
2.5
0.1
0.3
0.1
500
Maximum
1
-
100
-
-
-
1
-
Unit
A
mA
A
A
V/s
R04 www.ixysic.com
5
5 Page 
INTEGRATED CIRCUITS DIVISION
CPC7592
2. Functional Description
2.1 Introduction
2.1.1 CPC7592xA and CPC7592xB Logic States
• Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
• Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and loop test
switches SW5 and SW6 closed.
• All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
2.1.2 CPC7592xC Logic States
• Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
• Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test/Monitor. Break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test switches SW5 and SW6 closed.
• Ringing Test. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 closed.
• All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
The CPC7592 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State control is via TTL
logic-level input so no additional driver circuitry is
required. The linear break switches SW1 and SW2
have exceptionally low RON and excellent matching
characteristics. The ringing switch, SW4, has a
minimum open contact breakdown voltage of 465 V at
+25C sufficiently high with proper protection to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
Integrated into the CPC7592 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
To protect the CPC7592 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7592
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7592 operates from a single +5 V supply.
This gives the device extremely low power
consumption in any state with virtually any range of
battery voltage. The battery voltage used by the
CPC7592 has a two fold function. It is used as a
reference and as a current source for the internal
integrated protection circuitry under surge conditions.
Second, it is used as a reference. In the event of
battery voltage loss, the CPC7592 enters the all-off
state.
2.2 Under Voltage Switch Lock Out Circuitry
2.2.1 Introduction
Smart logic in the CPC7592 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
VDD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising VDD and
when to assert the under voltage switch lock out
circuitry with a falling VDD. Any time unsatisfactory low
VDD conditions exist the lock out circuit overrides user
switch control by blocking the information at the
external input pins and conditioning internal switch
R04 www.ixysic.com
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CPC7592BA.PDF ] | |
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