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UPD42S17405L-A70 fiches techniques PDF

NEC - 3.3V OPERATION 16M-BIT DYNAMIC RAM

Numéro de référence UPD42S17405L-A70
Description 3.3V OPERATION 16M-BIT DYNAMIC RAM
Fabricant NEC 
Logo NEC 





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UPD42S17405L-A70 fiche technique
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD42S17405L, 4217405L
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, EDO
Description
The µPD42S17405L, 4217405L are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the µPD42S17405L can execute CAS before RAS self refresh.
The µPD42S17405L, 4217405L are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 4,194,304 words by 4 bits organization
• Single +3.3 V ±0.3 V power supply
• Fast access and cycle time
Part number
µPD42S17405L-A50, 4217405L-A50
µPD42S17405L-A60, 4217405L-A60
µPD42S17405L-A70, 4217405L-A70
Power
consumption
Active (MAX.)
660 mW
360 mW
324 mW
Access time
(MAX.)
50 ns
60 ns
70 ns
µPD42S17405L can execute CAS before RAS self refresh
R/W cycle time
(MIN.)
84 ns
104 ns
124 ns
EDO (Hyper page mode)
cycle time (MIN.)
20 ns
25 ns
30 ns
Part number
Refresh cycle
µPD42S17405L 2,048 cycles/128 ms
µPD4217405L 2,048 cycles/32 ms
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
Power consumption
at standby (MAX.)
0.54 mW
(CMOS level input)
1.8 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M10068EJ6V0DS00 (6th edition)
Date Published January 1997 N
Printed in Japan
The mark shows major revised points.
©
1995

PagesPages 30
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