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PDF MAX5679ETJ Data sheet ( Hoja de datos )
| Número de pieza | MAX5679ETJ | |
| Descripción | Digitally Programmable LCD Gamma Reference Generator | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-4058; Rev 0; 3/08
Digitally Programmable LCD Gamma Reference
Generator with Digital Voltage Reference
General Description
The MAX5679 digitally programmable LCD gamma refer-
ence generator provides 18 buffered channels for biasing
LCD column drivers. The device provides 14 outputs of
8-bit programmable gamma reference voltage derived
from four externally applied reference voltages, and four
buffered outputs of the same externally applied reference
voltages. An I2C serial interface programs the 14 upper
and lower range gamma buffer outputs independently.
The MAX5679 features a digitally programmable volt-
age reference (DVR) with 7-bit adjustable current sink
to set the LCD common backplane (VCOM) voltage.
The MAX5679 includes a power-on reset (POR) function
that configures all 14 programmable gamma outputs to
predetermined levels upon initial power-up.
The MAX5679 is available in a 5mm x 5mm, 32-pin
TQFN package and is specified over the -40°C to
+85°C extended temperature range.
Applications
TFT-LCD Panels for Flat Screen TVs
TFT-LCD Panels for Desktop Monitors
TOP VIEW
Pin Configuration
32 31 30 29 28 27 26 25
OUT_REFU_H 1
24 GND
AVDD 2
DVDD 3
A0 4
SDA 5
MAX5679
23 REFL_L
22 REFL_H
21 SET
20 DVR
SCL 6
19 REFU_L
GND 7
18 REFU_H
OUT_REFL_L 8
17 AVDD
9 10 11 12 13 14 15 16
Features
♦ 7-Bit Adjustable VCOM Calibrator (DVR)
♦ 14 Programmable Gamma Outputs for LCD
Column Driver ICs
8-Bit DAC Resolution for Upper and Lower
Range Outputs
Maximum Output Swing of (AVDD - 0.2V)
(OUT1–OUT7)
Minimum Output Swing of (GND + 0.2V)
(OUT8–OUT14)
♦ Four Independent Reference Inputs
♦ Four Independent Buffered Reference Outputs
♦ 9V to 16.5V Analog Supply
♦ 2V to 5.5V Digital Supply
♦ 400kHz I2C-Compatible Serial Interface
♦ Pin-Selectable I2C Address Bit Allows
Two Slave IDs
♦ Backward Compatible with the MAX5678
Ordering Information
PART
TEMP RANGE
MAX5679ETJ+ -40°C to +85°C
+Denotes a lead-free package.
*EP = Exposed pad.
PIN-
PACKAGE
PKG
CODE
32 TQFN-EP*
(5mm x 5mm)
T3255+4
Gamma DAC Transfer Function
REFU_H
REFU_H
UPPER DAC
BLOCK
OUT1–OUT7
REFU_L
REFL_H
LOWER DAC
BLOCK
OUT8–OUT14
REFL_L
THIN QFN
(5mm x 5mm x 0.80mm)
0
GAMMA DAC DIGITAL CODE
255
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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1 page  
Digitally Programmable LCD Gamma Reference
Generator with Digital Voltage Reference
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 9V to 16.5V, DVDD = 2V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Data Hold Time
Data Setup Time
SDA/SCL Receiving
Rise Time
SYMBOL
tHD;DAT
tSU;DAT
tr
CONDITIONS
MIN
0
100
20 +
Cb/10
TYP
MAX
900
300
UNITS
ns
ns
ns
SDA/SCL Receiving
Fall Time
tf
20 +
Cb/10
300 ns
SDA Transmitting
Fall Time
STOP Setup Time
Bus Capacitance
Suppressed Spike
Pulse Width
tf
tSU;STO
Cb
tsp
DVDD = 2V to 2.7V
DVDD = 2.7V to 5.5V
20 +
Cb/10
0.6
10
10
250 ns
µs
100
pF
400
50 ns
Note 1: Specifications at TA = +85°C are guaranteed by production testing. Specifications at TA = -40°C and TA = +25°C are guaran-
teed by design and characterization.
Note 2: Error from the ideal output defined by the transfer function in the Gamma DAC Transfer Functions section.
Note 3: Due to power dissipation limits, not all outputs can source/sink IOUT (max) simultaneously.
Note 4: RS is a series resistor between the amplifier output and CL. The amplifier should be stable under this condition.
Note 5: The lower three codes, 0–2, are hardwired to give the same value as code two. This eliminates a zero-current condition in the
DVR output.
Note 6: Keep the minimum current into DVR > 10µA, and maximum current into DVR < 250µA over all codes.
Note 7: AVDD > 20V is a stress test. Functionality and spec compliance not guaranteed above 16.5V.
_______________________________________________________________________________________ 5
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5 Page 
Digitally Programmable LCD Gamma Reference
Generator with Digital Voltage Reference
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to signal the receipt of its address and each
byte of data (Figure 5). Each byte transferred thus
effectively requires nine clock pulses. The master gen-
erates the 9th clock pulse, and the recipient pulls down
SDA during the acknowledge clock pulse, ensuring the
SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the
MAX5679, the device generates the acknowledge bit
because the MAX5679 is the recipient. When the
MAX5679 is transmitting to the master, the master gen-
erates the acknowledge bit because the master is the
recipient. If the master fails to provide an acknowledge
bit during a read from the MAX5679, the MAX5679
interface ceases to provide data and waits for a new
START condition and a valid address. Not acknowledg-
ing by the master is a legitimate way to terminate read-
ing from the MAX5679; no STOP condition is necessary
afterwards.
START
CONDITION
SCL
SDA BY
TRANSMITTER
SDA BY
RECEIVER S
1
Figure 5. Acknowledge
CLOCK PULSE
FOR ACKNOWLEDGE
2 89
I2C Compatibility
The MAX5679 is fully compatible with existing I2C sys-
tems. The interface supports both standard (100kHz)
and fast (400kHz) data-transfer modes. The MAX5679
does not respond to a general call address.
Slave Address
The MAX5679 has a 7-bit long slave address (Table 1).
The 8th bit following the 7-bit slave address is the R/W
bit. The R/W bit is low for a write command or high for a
read command.
Bits B7 through B2 of the MAX5679 slave address are
set to 111010. Address input, A0, controls the slave
address bit, B1. Connect A0 to DVDD or GND. The
MAX5679 provides two possible slave addresses
(Table 1). An interface can control two MAX5679
devices independently.
The address input A0 can be driven dynamically.
Ensure that the bit value is stable in the address
sequence. The MAX5679 interface compares each
address value bit-by-bit to allow the interface to power
down in the event of a bus cycle that does not address
the MAX5679.
Write Data Format
Send a START condition followed by the 7-bit slave
address of the device with the R/W bit reset to 0 and
one or more data bytes to initiate a write command. The
MAX5679 supports two timing modes referred to as
Table 1. Slave Address
B7 B6 B5 B4 B3 B2 B1 B0
1 1 1 0 1 0 A0 R/W
______________________________________________________________________________________ 11
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