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PDF Si4032-B1 Data sheet ( Hoja de datos )
| Número de pieza | Si4032-B1 | |
| Descripción | ISM TRANSMITTER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si4030/31/32-B1
Si4030/31/32 ISM TRANSMITTER
Features
Frequency range
240–930 MHz (Si4031/32)
900–960 MHz (Si4030)
Output Power Range
+1 to +20 dBm (Si4032)
–8 to +13 dBm (Si4030/31)
Low Power Consumption
Si4032
85 mA @ +20 dBm
Si4030/31
30 mA @ +13 dBm
Data Rate = 0.123 to 256 kbps
FSK, GFSK, and OOK modulation
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Wake-up timer
Integrated 32 kHz RC or 32 kHz
XTAL
Integrated voltage regulators
Configurable packet handler
TX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
Low BOM
Power-on-reset (POR)
Applications
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Wireless PC peripherals
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Description
Silicon Laboratories’ Si4030/31/32 devices are highly integrated, single-chip
wireless ISM transmitters. The high-performance EZRadioPRO® family includes a
complete line of transmitters, receivers, and transceivers allowing the RF system
designer to choose the optimal wireless part for their application.
The Si4030/31/32 offers advanced radio features including continuous frequency
coverage from 240–960 MHz with adjustable power output levels of –8 to
+13 dBm on the Si4030/31 and +1 to +20 dBm on the Si4032. Power adjustments
are made in 3 dB steps. The Si4030/31/32’s high level of integration offers
reduced BOM cost while simplifying the overall system design. The Si4032’s
Industry leading +20 dBm output power ensures extended range and improved
link performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte TX FIFO, and automatic packet handling reduce overall current
consumption and allow the use of lower-cost system MCUs. An integrated
temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs
further reduce overall system cost and size.
The direct digital transmit modulation and automatic PA power ramping ensure
precise transmit modulation and reduced spectral spreading ensuring compliance
with global regulations including FCC, ETSI, and ARIB regulations.
An easy-to-use calculator is provided to quickly configure the radio settings,
simplifying customer's system design and reducing time to market.
Ordering Information:
See page 53.
Pin Assignments
Si4030/31/32
VDD_RF 1 20 19 18 17 16
TX 2
15 SCLK
NC 3
NC 4
GND
PAD
14 SDI
13 SDO
NC 5
12 VDD_DIG
6 7 8 9 10 11 NC
Patents pending
Rev 1.1 1/10
Copyright © 2010 by Silicon Laboratories
Si4030/31/32
1 page  
LIST OF FIGURES
Si4030/31/32-B1
Figure 1. SPI Timing.................................................................................................................. 15
Figure 2. SPI Timing—READ Mode ..........................................................................................16
Figure 3. SPI Timing—Burst Write Mode .................................................................................. 16
Figure 4. SPI Timing—Burst Read Mode .................................................................................. 16
Figure 5. State Machine Diagram.............................................................................................. 17
Figure 6. TX Timing................................................................................................................... 21
Figure 7. Frequency Deviation .................................................................................................. 25
Figure 8. FSK vs. GFSK Spectrums..........................................................................................27
Figure 9. Microcontroller Connections....................................................................................... 30
Figure 10. PLL Synthesizer Block Diagram............................................................................... 31
Figure 11. FIFO Threshold ........................................................................................................34
Figure 12. Packet Structure....................................................................................................... 35
Figure 13. Multiple Packets in TX Packet Handler .................................................................... 36
Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37
Figure 15. Manchester Coding Example ...................................................................................37
Figure 16. POR Glitch Parameters............................................................................................ 39
Figure 17. General Purpose ADC Architecture ......................................................................... 41
Figure 18. Temperature Ranges using ADC8 ........................................................................... 43
Figure 19. WUT Interrupt and WUT Operation.......................................................................... 46
Figure 20. Si4031 Reference Design Schematic ...................................................................... 48
Figure 21. 20-Pin Quad Flat No-Lead (QFN) ............................................................................54
Figure 22. PCB Land Pattern .................................................................................................... 55
Rev 1.1
5
5 Page 
Si4030/31/32-B1
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Parameter
Symbol
Conditions
Min Typ Max Units
Rise Time
TRISE 0.1 x VDD to 0.9 x VDD, CL= 5 pF
—
— 8 ns
Fall Time
TFALL 0.9 x VDD to 0.1 x VDD, CL= 5 pF
—
— 8 ns
Input Capacitance
CIN
— — 1 pF
Logic High Level Input Voltage
VIH
VDD – 0.6 —
—
V
Logic Low Level Input Voltage
VIL
— 0.6
V
Input Current
IIN
0<VIN< VDD
–100
— 100 nA
Logic High Level Output
Voltage
VOH
IOH<1 mA source, VDD=1.8 V VDD – 0.6 —
—
V
Logic Low Level Output Voltage VOL
IOL<1 mA sink, VDD=1.8 V
—
— 0.6
V
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions"
section on page 13.
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter
Symbol
Conditions
Min Typ Max Units
Rise Time
TRISE
0.1 x VDD to 0.9 x VDD,
— — 8 ns
CL= 10 pF, DRV<1:0>=HH
Fall Time
TFALL
0.9 x VDD to 0.1 x VDD,
— — 8 ns
CL= 10 pF, DRV<1:0>=HH
Input Capacitance
CIN
— — 1 pF
Logic High Level Input Voltage
VIH
VDD – 0.6 —
V
Logic Low Level Input Voltage
VIL
—
— 0.6
V
Input Current
IIN
0<VIN< VDD
–100
— 100 nA
Input Current If Pullup is Activated IINP
VIL=0 V
5 — 25 µA
Maximum Output Current
IOmaxLL
DRV<1:0>=LL
0.1 0.5 0.8 mA
IOmaxLH
DRV<1:0>=LH
0.9 2.3 3.5 mA
IOmaxHL
DRV<1:0>=HL
1.5 3.1 4.8 mA
IOmaxHH
DRV<1:0>=HH
1.8 3.6 5.4 mA
Logic High Level Output Voltage
VOH
IOH< IOmax source,
VDD=1.8 V
VDD – 0.6 —
—
V
Logic Low Level Output Voltage
VOL
IOL< IOmax sink,
VDD=1.8 V
—
— 0.6
V
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions"
section on page 13.
Rev 1.1
11
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