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PDF FDMA3028N Data sheet ( Hoja de datos )

Número de pieza FDMA3028N
Descripción Dual N-Channel PowerTrench MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FDMA3028N
June 2011
Dual N-Channel PowerTrench® MOSFET
30 V, 3.8 A, 68 mΩ
Features
General Description
„ Max rDS(on) = 68 mΩ at VGS = 4.5 V, ID = 3.8 A
„ Max rDS(on) = 88 mΩ at VGS = 2.5 V, ID = 3.4 A
„ Max rDS(on) = 123 mΩ at VGS = 1.8 V, ID = 2.9 A
„ Low profile - 0.8 mm maximum - in the new package
MicroFET 2x2 mm
This device is designed specifically as a single package solution
for dual switching requirements in cellular handset and other
ultra-portable applications. It features two independent
N-Channel MOSFETs with low on-state resistance for minimum
conduction losses. The MicroFET 2x2 package offers
exceptional thermal performance for its physical size and is well
suited to linear mode applications.
„ RoHS Compliant
PIN 1
S1 G1 D2
D1 D2
S1 1
G1 2
6 D1
5 G2
D1 G2 S2
D2 3
Top Bottom
4 S2
MicroFET 2x2
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Pulsed
Power Dissipation
Power Dissipation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 1a)
(Note 1b)
Ratings
30
±12
3.8
16
1.5
0.7
-55 to +150
Units
V
V
A
W
°C
RθJA
Thermal Resistance for Single Operation, Junction to Ambient
Thermal Resistance for Single Operation, Junction to Ambient
Thermal Resistance for Dual Operation, Junction to Ambient
Thermal Resistance for Dual Operation, Junction to Ambient
Thermal Resistance for Single Operation, Junction to Ambient
Thermal Resistance for Dual Operation, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1d)
(Note 1e)
(Note 1f)
86
173
69
151
160
133
°C/W
Device Marking
328
Device
FDMA3028N
Package
MicroFET 2X2
Reel Size
7 ’’
Tape Width
8 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMA3028N Rev.C2
1
www.fairchildsemi.com

1 page




FDMA3028N pdf
Typical Characteristics TJ = 25°C unless otherwise noted
5
ID = 3.8 A
4
3
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
1
0
01234
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
500
Ciss
100
Coss
Crss
f = 1 MHz
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
20
10
100 μs
1
1 ms
THIS AREA IS
LIMITED BY rDS(on)
0.1 SINGLE PULSE
TJ = MAX RATED
RθJA = 173 oC/W
TA = 25 oC
0.01
0.1
1
10 ms
100 ms
1s
10 s
DC
10 100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
100
SINGLE PULSE
RθJA = 173 oC/W
TA = 25 oC
10
1
0.5
10-4
10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 10. Single Pulse Maximum
Power Dissipation
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01
0.005
10-4
10-3
SINGLE PULSE
RθJA = 173 oC/W
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
10
100
Figure 11. Junction-to-Ambient Transient Thermal Response Curve
1000
©2011 Fairchild Semiconductor Corporation
FDMA3028N Rev.C2
5
www.fairchildsemi.com

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