DataSheetWiki


MPC92439FA fiches techniques PDF

IDT - LVPECL Clock Syntheesizer

Numéro de référence MPC92439FA
Description LVPECL Clock Syntheesizer
Fabricant IDT 
Logo IDT 





1 Page

No Preview Available !





MPC92439FA fiche technique
900MHz, Low Voltage,
LVPECL Clock Syntheesizer
MPC92439
DATA SHEET
The MPC92439 is a 3.3 V compatible, PLL based clock synthesizer targeted for high
performance clock generation in mid-range to high-performance telecom, networking and
computing applications. With output frequencies from 3.125 MHz to 900 MHz and the
support of differential LVPECL output signals the device meets the needs of the most
demanding clock applications.
900MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
Features
• 3.125 MHz to 900 MHz synthesized clock output signal
• Differential LVPECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference input
FN SUFFIX(1)
28-LEAD PLCC PACKAGE
CASE 776-02
• 3.3V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 28-PLCC and 32-LQFP packaging
• 28-Lead and 32-lead Pb-free packages available
EI SUFFIX(2)
28-LEAD PLCC PACKAGE
CASE 776-02
• SiGe Technology
• Ambient temperature range 0°C to + 70°C
• Pin and function compatible to the MC12439 and MPC9239
FA SUFFIX(1)
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency
32-LEAD LQFP PACKAGE
CASE 873A-03
reference. The frequency of the internal crystal oscillator or external reference clock signal is
multiplied by the PLL. The VCO within the PLL operates over a range of 400 to 900 MHz. Its
output is scaled by a divider that is configured by either the serial or parallel interfaces. The
crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N de-
termine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to
AC SUFFIX(2)
32-LEAD LQFP PACKAGE
CASE 873A-03
be M times the reference frequency by adjusting the VCO control voltage. Note that for
some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL
will be stable if the VCO frequency is within the specified VCO frequency range (400 to 900
MHz). The M-value must be programmed by the serial or parallel interface.
K SUFFIX
32-LEAD VFQFN PACKAGE
Pb-FREE PACKAGE
The PLL post-divider N is configured through either the serial or the parallel interfaces,
and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance
of the part while providing a 50% duty cycle. The output driver is driven differentially from
the output divider, and is capable of driving a pair of transmission lines terminated 50to
VCC – 2.0V. The positive supply voltage for the internal PLL is separated from the power
supply for the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses
the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recom-
Notes:
(1) FN, FA suffix: leaded terminations
(2) EI, AC suffix: lead-free, RoHS-compliant, EPP
ORDERING INFORMATION
Device
Package
mended on system reset to hold the P_LOAD input LOW until power becomes valid. On the MPC92439EI
PLCC-28 (Pb-Free)
LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface
has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and
N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial inter-
MPC92439FA
MPC92439AC
LQFP-32
LQFP-32 (Pb-Free)
face centers on a twelve bit shift register. The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in
the AC Characteristics section of this document. The configuration latches will capture the
P R O P O S E DMPC92439KLF
VFQFN-32 (Pb-Free)
value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST
output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it
is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16.
The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon
de-assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
MPC92439 REVISION 4 OCTOBER 27, 2009
1
©2009 Integrated Device Technology, Inc.

PagesPages 15
Télécharger [ MPC92439FA ]


Fiche technique recommandé

No Description détaillée Fabricant
MPC92439FA LVPECL Clock Syntheesizer IDT
IDT

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche