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PDF MPC92469 Data sheet ( Hoja de datos )
| Número de pieza | MPC92469 | |
| Descripción | 400 MHz Low Voltage PECL Clock Synthesizer w/Spread Spectrum | |
| Fabricantes | IDT | |
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400 MHz Low Voltage PECL
Clock Synthesizer w/Spread
Spectrum
MPC92469
The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance tele-
com, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
400 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
w/SPREAD SPECTRUM
Features
• 25 MHz to 400 MHz synthesized clock output signal
• Differential PECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Spread Spectrum output for EMI reduction
• 3.3 V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32-lead LQFP packaging
• 32-lead Pb-free package available
• SiGe Technology
• Ambient temperature range 0°C to +70°C
• Pin compatible to the MC12429, MPC9229, MPC92429, and ICS84329
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 400
to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator
frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2⋅M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a eighteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAM-
MING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
1
MPC92469REV 4 JANUARY 23, 2007
1 page  
MPC92469
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
Symbol
Characteristics
Min
fXTAL
fVCO
fMAX
Crystal Interface Frequency Range
VCO Frequency Range(2)
Output Frequency
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
12
400
200
100
50
25
DC Output Duty Cycle
48
tr, tf Output Rise/Fall Time
0.05
Typ
50
Max Unit Condition
20 MHz
800 MHz
400 MHz
200 MHz
100 MHz
50 MHz
52 %
0.3 ns 20% to 80%
fS_CLOCK
tP,MIN
tS
tS
tJIT(CC)
Serial Interface Programming Clock Frequency(3)
Minimum Pulse Width
(S_LOAD, P_LOAD)
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
Cycle-to-Cycle Jitter
50
20
20
20
20
20
10 MHz
ns
ns
ns
ns
ns
ns
50 ps N ≠ 8
tJIT(PER) Period Jitter
50 ps N ≠ 8
tLOCK
SSMfmod
SSMdev
Maximum PLL Lock Time
Spread Spectrum Modulation Frequency
Spread Spectrum Modulation Deviation
SS[3:0] = 0001
SS[3:0] = 1001
32
±0.30
-0.3
10
±0.5
-0.5
ms
kHz fXTAL = 16 MHz
% fout = 300 MHz
% fXTAL = 16 MHz
1. AC characteristics apply for parallel output termination of 50 Ω to VTT.
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL x M ÷ 8.
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
5
MPC92469REV 4 JANUARY 23, 2007
5 Page 
MPC92469
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
Figure 9. Package Drawing for 32 Lead LQFP
Table 13. Package Dimensions for 32Lead LQFP
SYMBOL
N
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
θ
ccc
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
MINIMUM
NOMLINAL
32
-- --
0.05 --
1.35 1.40
0.30 0.37
0.09 --
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.45 0.60
0˚ --
-- --
MAXMIMUM
1.60
0.15
1.45
0.45
0.20
0.75
7˚
0.10
IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
11
MPC92469REV 4 JANUARY 23, 2007
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MPC92469.PDF ] | |
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