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PDF MPC9259 Data sheet ( Hoja de datos )
| Número de pieza | MPC9259 | |
| Descripción | 900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
Freescale Semiconductor, Inc. Order Number: MPC9259/D
SEMICONDUCTOR TECHNICAL DATA
Rev 0, 12/2002
Preliminary Information
900 MHz Low Voltage LVDS
Clock Synthesizer
The MPC9259 is a 3.3V compatible, PLL based clock synthesizer
targeted for high performance clock generation in mid-range to
high-performance telecom, networking and computing applications. With
output frequencies from 50 MHz to 900 MHz and the support of differential
LVDS output signals the device meets the needs of the most demanding
clock applications.
Features
• 50 MHz to 900 MHz synthesized clock output signal
• Differential LVDS output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference input
• 3.3V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32 Pin LQFP Package
• SiGe Technology
• Ambient temperature range 0°C to + 70° C
MPC9259
900 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range
of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.
The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be
programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this
document. The configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input.
See the programming section for more information. The TEST output reflects various internal node values, and is controlled by
the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST
output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked
by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2002
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
MPC9259
Table 6. DC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 70°C)a
Symbol
Characteristics
Min
Typ
Max Unit
Condition
LVCMOS control inputs (FREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:6], N[0:1], OE)
VIH Input high voltage
VIL Input low voltage
IIN Input Currentb
Differential clock output FOUT
2.0
VCC + 0.3 V
LVCMOS
0.8 V LVCMOS
±200
µA VIN = VCC or GND
VPP
Output Differential Voltage (peak–to–peak)
VOS
Output Offset Voltage
Test and diagnosis output TEST
250
1125
1275
mV LVDS
mV LVDS
VOH
Output High Voltage
VOL
Output Low Voltage
Supply current
2.0 V IOH =-0.8 mA
0.55 V IOL = 0.8 mA
ICC_PLL Maximum PLL Supply Current
ICC Maximum Supply Current
a. All AC characteristics are design targets and subject to change upon device characterization.
b. Inputs have pull-down resistors affecting the input current.
20
110
mA VCC_PLL Pins
mA All VCC Pins
Table 7. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 70°C)a
Symbol
Characteristics
Min
Typ
Max Unit
Condition
fXTAL
fVCO
fMAX
fS_CLOCK
tP,MIN
DC
Crystal interface frequency range
VCO frequency rangeb
Output Frequency
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
Serial interface programming clock frequencyc
Minimum pulse width
(S_LOAD, P_LOAD)
Output duty cycle
10
800
400
200
100
50
0
50
45
20 MHz
1800
MHz
900
450
225
112.5
MHz
MHz
MHz
MHz
PWR_DOWN = 0
10 MHz
ns
50 55 %
tr, tf Output Rise/Fall Time
tS Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
0.05
20
20
20
TBD
ns 20% to 80%
ns
ns
ns
tS Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
tJIT(CC) Cycle-to-cycle jitter
RMS (1 σ)d
TBD
TBD
ps
tJIT(PER) Period Jitter
RMS (1 σ)
±25 ps
tLOCK
Maximum PLL Lock Time
10 ms
a. All AC characteristics are design targets and subject to change upon device characterization.
b. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ 2 ⋅ M.
c. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See application section for more details.
d. See application section for a jitter calculation for other confidence factors than 1 σ.
TIMING SOLUTIONS
For MorGeoIntfoo:rwmwa5twio.fnreOenscTahlies.cPoromduct,
MOTOROLA
5 Page 
Freescale Semiconductor, Inc.
NOTES
MPC9259
TIMING SOLUTIONS
For MorGeoIntfoo:rwmwa1t1wio.fnreOenscTahlies.cPoromduct,
MOTOROLA
11 Page | ||
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| PDF Descargar | [ Datasheet MPC9259.PDF ] | |
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