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PDF RL78L12 Data sheet ( Hoja de datos )
| Número de pieza | RL78L12 | |
| Descripción | MCU | |
| Fabricantes | Renesas | |
| Logotipo |  |
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Datasheet
RL78/L12
R01DS0157EJ0100
RENESAS MCU
Rev.1.00
2013.01.31
Integrated LCD controller/driver, True Low Power Platform (as low as 62.5 µA/MHz, and 0.64 µA for RTC +
LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
• Halt (RTC + LVD): 0.64 µA
• Supports snooze
• Operating: 62.5 µA/MHz
• LCD operating current (Capacitor split method): 0.12
µA
• LCD operating current (Internal voltage boost
method): 0.63 µA (VDD = 3.0 V)
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 8 KB to 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with flash shield window function
Data Flash Memory
• Data flash with background operation
• Data flash size: 2 KB size
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 1 KB and 1.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 24 MHz with +/− 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (−20°C to 85°C)
• Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8
MHz, 4 MHz & 1 MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
LCD Controller/Driver
• Up to 35 seg x 8 com or 39 seg x 4 com
• Supports capacitor split method, internal voltage
boost method and resistance division method
• Supports waveform types A and B
• Supports LCD contrast adjustment (16 steps)
• Supports LCD blinking
Data Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
• Up to 1 × I2C multi-master
• Up to 2 × CSI/SPI (7-, 8-bit)
• Up to 1 × UART (7-, 8-, 9-bit)
• Up to 1 × LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 10 channels, 10-bit resolution, 2.1 µs
conversion time
• Supports 1.6 V
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock frequency detection
• ADC self-test
General Purpose I/O
• 5V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: −40 °C to +85 °C
Package Type and Pin Count
From 7mm x 7mm to 12mm x 12mm
QFP: 32, 44, 48, 52, 64
QFN: 64
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 1 of 77
1 page  
RL78/L12
1.3.2 44-pin products
• 44-pin plastic LQFP (10 × 10)
1. OUTLINE
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P141/TI00/PCLBUZ1/SEG26
33 32 31 30 29 28 27 26 25 24 23
34 22
35 21
36 20
37 19
38 18
39 17
40 16
41 15
42 14
43 13
44 12
1 2 3 4 5 6 7 8 9 10 11
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 5 of 77
5 Page 
RL78/L12
1.5 Block Diagram
1.5.1 32-pin products
TI00/P13
TO00/P140
TI01/TO01/P30
TI02/TO02/P17
(TI02/TO02/P12)
TI07/TO07/P10
TIMER ARRAY
UNIT0 (8ch)
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
<R>
LOW-SPEED
ON-CHIP
OSCILLATOR
REAL-TIME
CLOCK
12- BIT INTERVAL
TIMER
WINDOW
WATCHDOG
TIMER
SEG0, SEG4 to SEG6,
SEG19 to SEG21,
SEG27 to SEG32
COM0 to COM3, COMEXP
VL1, VL2, VL4
CAPH
CAPL
13
5
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
RxD0/P11
TxD0/P12
SCK00/P10
SI00/P11
SO00/P12
SCK01/P15
SI01/P16
SO01/P17
SERIAL ARRAY
UNIT0 (2ch)
UART0
CSI00
CSI01
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
BCD
ADJUSTMENT
1. OUTLINE
A/D CONVERTER
2 ANI0/P20, ANI1/P21
2 ANI18/P13, ANI19/P14
AVREFP/P20
AVREFM/P21
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
RAM
VDD VSS TOOLRxD/P11,
TOOLTxD/P12
DIRECT MEMORY
ACCESS CONTROL
CRC
PORT 1
PORT 2
PORT 3
PORT 4
8 P10 to P17
2 P20, P21
P30
P40
PORT 6
2 P60, P61
PORT 12
PORT 13
2 P126, P127
2 P121, P122
P137
PORT 14
P140
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
KEY RETURN
PCLBUZ0/P140
3 KR0/P12 to KR2/P10
KR3/P140
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
ON-CHIP DEBUG
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
VOLTAGE
REGULATOR
TOOL0/P40
RESET
X1/P121
X2/EXCLK/P122
REGC
INTERRUPT
CONTROL
INTP0/P137
INTP1/P15(INTP1/P10),
2 INTP2/P16(INTP2/P11)
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 11 of 77
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet RL78L12.PDF ] | |
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