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Número de pieza | MC14046B | |
Descripción | Phase Locked Loop | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
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SEMICONDUCTOR TECHNICAL DATA
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators, a
voltage–controlled oscillator (VCO), source follower, and zener diode. The
comparators have two common signal inputs, PCAin and PCBin. Input PCAin
can be used directly coupled to large voltage signals, or indirectly coupled
(with a series capacitor) to small voltage signals. The self–bias circuit
adjusts small voltage signals in the linear region of the amplifier. Phase
comparator 1 (an exclusive OR gate) provides a digital error signal PC1out,
and maintains 90° phase shift at the center frequency between PCAin and
PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading
edge sensing logic) provides digital error signals, PC2out and LD, and
maintains a 0° phase shift between PCAin and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout whose
frequency is determined by the voltage of input VCOin and the capacitor and
resistors connected to pins C1A, C1B, R1, and R2. The source–follower
output SFout with an external resistor is used where the VCOin signal is
needed but no loading can be tolerated. The inhibit input Inh, when high,
disables the VCO and source follower to minimize standby power
consumption. The zener diode can be used to assist in power supply
regulation.
Applications include FM and FSK modulation and demodulation, fre-
quency synthesis and multiplication, frequency discrimination, tone decod-
ing, data synchronization and conditioning, voltage–to–frequency
conversion and motor speed control.
• Buffered Outputs Compatible with MHTL and Low–Power TTL
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 to 18 V
• Pin–for–Pin Replacement for CD4046B
• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited
• Phase Comparator 2 switches on Rising Edges and is not Duty Cycle
Limited
BLOCK DIAGRAM
PCAin 14
PCBin 3
VCOin 9
VDD = PIN 16
VSS = PIN 8
INH 5
SELF BIAS
CIRCUIT
VSS
PHASE
COMPARATOR 1
PHASE
COMPARATOR 2
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
SOURCE FOLLOWER
2 PC1out
13 PC2out
1 LD
4 VCOout
11 R1
12 R2
6 C1A
7 C1B
10 SFout
15 ZENER
MC14046B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
LD
PC1out
PCBin
VCOout
INH
C1A
C1B
VSS
1
2
3
4
5
6
7
8
16 VDD
15 ZENER
14 PCAin
13 PC2out
12 R2
11 R1
10 SFout
9 VCOin
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14046B
1
1 page PCAin
14
@ FREQUENCY f′ 3
PCBin
PHASE
COMPARATOR
2 OR 13
PC1out
OR
PC2out
VCOin
9 SOURCE 10
FOLLOWER
SFout
RSF
EXTERNAL
LOW–PASS
FILTER
EXTERNAL
÷N
COUNTER
9 VCO
11 12
R1 R2
6
CIA
CI
4
7
CIB
VCOout
@ FREQUENCY Nf′ = f
Typical Low–Pass Filters
[ Ǹ(a) R3
(a) R3
INPUT
OUTPUT
INPUT
OUTPUT
C2
2fC
p1
2 p fL
R3 C2
R4
C2
Typically:
+R4 C2
6N
fmax
–
N
2pD
f
) +(R3
3, 000W) C2
100NDf
fmax2
–
R4
C2
∆ f = fmax – fmin
NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint to ground. The value for
^CC should be such that the corner frequency of this network does not significantly affect ωn. In Figure B, the ratio of R3 to R4 sets the
damping, R4 (0.1)(R3) for optimum results.
LOW–PASS FILTER
Definitions: N = Total division ratio in feedback loop
Kφ = VDD/π for Phase Comparator 1
Kφ = VDD/4 π for Phase Comparator 2
+KVCO
2 p D fVCO
VDD – 2 V
^for a typical design ωn
2 p fr (at phase detector input)
10
^ζ 0.707
+ ǸFilter A
wn
KfKVCO
NR3C2
+z
Nwn
2KfKVCO
+ )F(s)
1
R3C2S
1
+ Ǹ )Filter B
wn
KfKVCO
NC2(R3 R4)
+ )z
0.5 wn (R3C2
N
KfKVCO)
+ ) ) )F(s)
R3C2S 1
S(R3C2 R4C2)
1
PCAin
PCBin
PC1out
VCOin
Waveforms
Phase Comparator 1
VDD
VSS
VOH
VOL
VOH
VOL
VOH
VOL
PCAin
PCBin
LD
PC2out
VCOin
Phase Comparator 2
Note: for further information, see:
(1) F. Gardner, “Phase–Lock Techniques”, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, “Miniature RC Filters Using Phase–Locked Loop”, BSTJ, May, 1965.
(3) Garth Nash, “Phase–Lock Loop Design Fundamentals”, AN–535, Motorola Inc.
(4) A. B. Przedpelski, “Phase–Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.
Figure 3. General Phase–Locked Loop Connections and Waveforms
VDD
VSS
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
MOTOROLA CMOS LOGIC DATA
MC14046B
5
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet MC14046B.PDF ] |
Número de pieza | Descripción | Fabricantes |
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