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PDF R1LV1616RBG-7SI Data sheet ( Hoja de datos )
| Número de pieza | R1LV1616RBG-7SI | |
| Descripción | 16Mb superSRAM | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Preliminary
R1LV1616R Series
16Mb superSRAM (1M wordx16bit)
This product is under development and its specification
might be changed without any notice.
REJ03C0101-0002Z
Rev.0.02
2003.10.24
Description
The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit,
fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies.
The R1LV1616R Series is suitable for memory applications where a simple interfacing , battery operating and
battery backup are the important design objectives.
The R1LV1616R Series is packaged in a 52pin micro thin small outline mount device[µTSOP / 10.79mm x
10.49mm with the pin-pitch of 0.4mm] or a 48balls fine pitch ball grid array [f-BGA / 7.5mmx8.5mm with the ball-pitch
of 0.75mm and 6x8 array] . It gives the best solution for a compaction of mounting area as well as flexibility of wiring
pattern of printed circuit boards.
Features
• Single 2.7-3.6V power supply
• Small stand-by current:4µA (3.0V, typ.)
• Smaller stand-by current by "Data retention mode"(“CS2"='L') : 1µA (3.0V, typ.)
• Data retention supply voltage =2.0V
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion by CS1#, CS2, LB# and UB#
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE# prevents data contention on the I/O bus
• Process technology: 0.15um CMOS
Rev.0.02 2003.10.24 page 1 of 16
1 page  
R1LV1616R Series
Preliminary This product is under development and its specification
might be changed without any notice.
Operating Table
CS1# CS2* 3 BYTE#* 2 LB# UB# WE# OE# DQ0~7
H H X X X X X High-Z
X L X X X X X High-Z
X H X H H X X High-Z
L H H L H L X Din
L H H L H H L Dout
DQ8~14
High-Z
High-Z
High-Z
High-Z
High-Z
DQ15
High-Z
High-Z
High-Z
High-Z
High-Z
Operation
Stand-by
Data
retention
Stand-by
Write in
lower byte
Read from
lower byte
L H H L H H H High-Z High-Z High-Z
L H H H L L X High-Z Din Din
L H H H L H L High-Z Dout Dout
Output disable
Write in
upper byte
Read from
upper byte
L H H H L H H High-Z High-Z High-Z
L
H
H
L L L X Din
Din
Din
L
H
H
L
L H L Dout
Dout
Dout
Output disable
Write
Read
L H H L L H H High-Z High-Z High-Z
Output disable
L H L L L L X Din High-Z A-1
L H L L L H L Dout High-Z A-1
Write
Read
L H L L L H H High-Z High-Z A-1
Output disable
Note 1,H:VIH L:VIL X: VIH or VIL
2, BYTE# pin supported by only TSOP type. When apply BYTE# =“L” ,please assign LB#=UB#=“L”.
*3 Notification about a new function of CS2 signal
R1LV1616R Series use CS2 signal to control the internal voltage for as 'Data retention mode'. In case of
conventional SRAM products, both CS1# and CS2 signals are used as control signals for device operation of active
and stand-by modes. In terms of R1LV1616R Series, CS1# is an ordinary function that controls device operation,
but CS2 function is to make a switch device status between 'Stand-by mode' and 'Data retention mode', based on
the input level of CS2 signal. In the concrete, when setting CS2 at a high level, a device status is changed from
'Data retention mode' to 'Stand-by mode'. And when setting CS2 at a low level, it's changed from 'Stand-by mode'
to 'Data retention mode'. The latter is a new function. During 'Data retention mode' with CS2='L', the reduction of
current consumption is achieved by turning off the internal voltage supply except memory cell array. Therefore in
case of using with CS2 signal as for 'back up control with battery' , it will be realized the most suitable system.
With regard to the detailed specifications for CS2 signal, please refer to the item of "Timing diagram" in p.11~p.14
and that of "Data retention characteristics" in p.15.
Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage relative to Vss
Vcc
Terminal voltage on any pin relation toVss
VT
Power dissipation
Operation temperature
PT
Topr
Storage temperature range
Tstg
Storage temperature range under bias
Tbias
Note 1: -3.0V in case of AC (Pulse width ≤ 30ns)
2:Maximum voltage is +4.6V
Value
-0.5 to +4.6
-0.5*1 to Vcc+0.3*2
0.7
-40 to + 85
-65 to + 150
-40 to + 85
Unit
V
V
W
ºC
ºC
ºC
Rev.0.02 2003.10.24 page 5 of 16
5 Page 
R1LV1616R Series
Preliminary This product is under development and its specification
might be changed without any notice.
Read Cycle
A0~19
(Word Mode)
A-1~19
(Byte Mode)
LB#,UB#
CS1#
CS2
Timing Waveform
tRC
Valid address
tAA
tBA
tPR*
tACS
tOH
tBHZ
tCHZ
OE#
tOE
WE# = "H" level
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
tOLZ
tCLZ
tBLZ
Note , About tPR, See Data Retention Characteristics p.15
tOHZ
Valid data
Rev.0.02 2003.10.24 page 11 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet R1LV1616RBG-7SI.PDF ] | |
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