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PDF UBA20260 Data sheet ( Hoja de datos )
| Número de pieza | UBA20260 | |
| Descripción | 600V driver IC | |
| Fabricantes | NXP Semiconductors | |
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UBA20260
600 V driver IC for step dimmable CFLs
Rev. 2 — 10 October 2011
Product data sheet
1. General description
The UBA20260 is a high-voltage integrated circuit designed to control high power
self-ballasted Compact Fluorescent Lamp (CFL) lighting applications. The UBA20260 is a
controller circuit with advanced features for step dimming and a lamp current controlled
boost feature for boosting cold (amalgam) CFLs.
The controller contains a half-bridge drive function for CFLs, a high-voltage level-shift
circuit with integrated bootstrap diode, an oscillator function, a current control function for
preheat and burn, a timer function and protection circuits. The UBA20260 is supplied
using the dV/dt current charge supply circuit from the half-bridge circuit.
Remark: The mains voltages given in this data sheet are AC voltages.
2. Features and benefits
2.1 Half-bridge features
Integrated high-voltage level-shift function with integrated bootstrap diode
2.2 Preheat and ignition features
Coil saturation protection during ignition
Adjustable preheat time
Adjustable preheat current
Ignition lamp current detection
2.3 Lamp boost features
Adjustable boost timing
Fixed boost current ratio of 1.5
Gradually boost to burn transition timing
1 page  
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
7. Functional description
7.1 Supply voltage
The UBA20260 is an IC for driving external half-bridge MOSFETs in self-ballasted
high-power CFLs. The UBA20260 has no dimming control input but instead, four preset
fixed dimming levels. Only minor adjustment of the presets is possible.
The UBA20260 is rated for a maximum continuous rectified mains voltage of 500 V (with
peak 600 V). The UBA20260 includes all functions necessary for preheat, ignition and
boost operation of the lamp. In addition, the IC includes the four-step dimming feature and
several protective features to safeguard CFL operation. The controller states are shown in
Figure 3.
VDD = 0
RESET STATE
HOLD = 0
VDD < VDD(rst)
VDD > VDD(rst)
VDD < VDD(rst)
START-UP STATE
VCP < Vth(rel)CP
(1)
POWER-DOWN STATE
PREHEAT STATE
VDD < VDD(stop)
preheat time
completed
IGNITION STATE
Ignition_Detected
BOOST AND BURN
STATES
(2)
(3)
HOLD STATE
HOLD = 1
(4)
(5)
(1) VDD < VDD(start) and (HOLD = 0 OR VCP < Vth(rel)CP).
(2) VDD < VDD(stop).
(3) (End of ignition time AND HOLD = 0) OR VDD < VDD(stop).
(4) End of ignition time AND HOLD = 1
(5) VCP < Vth(pd)CP, OR overcurrent fault time > 1⁄10 tph OR fbridge(max) detected in capacitive mode.
Fig 3. State diagram
001aam763
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
5 of 30
5 Page 
NXP Semiconductors
UBA20260
600 V driver IC for step dimmable CFLs
the supply voltage VDD rises between VDD(stop) and VDD(start). Typically, the supply current
is 2 mA when VDD falls between VDD(start) and VDD(stop). More current is drawn during the
fall in VDD because the internal analog supply is turned on when VDD > VDD(start). This
function enables the comparators to monitor the voltage on the CP pin and if the supply
voltage VDD falls below VDD(stop).
7.3 Oscillation and timing
7.3.1 Oscillator control
The internal oscillator is a VCO which generates a saw-tooth waveform between the
Vth(CF)max level and 0 V. Capacitor CCF, resistor Rext(RREF) and the voltage on the CI pin
determine the saw-tooth frequency. Rext(RREF) and CCF determine the minimum and
maximum switching frequencies. Their ratio is internally fixed. Two ratios are available,
the ratio between fbridge(max) and fbridge(min) is 2.5 and the ratio between fbridge(max) and
fbridge(bst)min is 4.6. The saw-tooth frequency is twice the half-bridge frequency.
Transistors HS (Q1) and LS (Q2) are switched to conducting at a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is shown in
Figure 8. The oscillator starts oscillating at fbridge(max). The non-overlap time between the
gate driver signals VGLS and VGHS is tno.
voltage
(V)
VCF
0
V(GHS-HBO)
0
VGLS
0
tdch
tno tno
VHBO
0
Fig 8. Saw-tooth, gate driver and half-bridge output signals
time (s)
001aam766
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
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