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PDF PI74ALVCH16500 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH16500 | |
| Descripción | 18-Bit Universal Bus Transceiver | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI74ALVCH16500 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
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PI74ALVCH165001122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
• PI74ALVCH16500 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-State
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74ALVCH16500 univeral bus transceiver is designed
for 2.3V to 3.6V Vcc operation.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latch- Enable (LEAB and LEBA), and clock (CLKAB
and CLKBA) inputs. For A- to-B data flow, the device operates in
the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CLKAB is held at a high or low logic level. If
LEAB is low, the A data is stored in the latch/flip-flop on the high-
to-low transition of CLKAB. Output-enable OEAB is active high.
When OEAB is high, the B-port outputs are active. When OEAB is
low, the B-port outputs are in the high-impedence state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The Output Enables are complementary
(OEAB is active HIGH and OEBA is active LOW).
To ensure the high-impedance state during power up or power
down, OEBA should be tied to Vcc through a pull-up resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the current-sinking/
current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
30
CLKBA
27
OEBA
3
A1
C1 1D
C1
1D
CLK
1D
C1
CLK
54
B1
TO 17 OTHER CHANNELS
1 PS8155A 11/06/00
1 page  
PI74ALVCH16500
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Timing Requirements over Operating Range
Parameters
Description
Conditions(1) VCC= 2.5V ± 0.2V
VCC= 2.7V
VCC= 3.3V ± 0.3V
Units
Min. Max. Min. Max. Min. Max.
fCLOCK Clock frequency
0 150 0 150 0 150 MHz
tW Pulse LE high
Duration CLK high or low
3.3 3.3 3.3
3.3 3.3 3.3
tSU Setup
time
Data before CLK ↓
Data before LE ↓, CLK high
Data before LE ↓, CLK low
CL = 50pF
RL = 500Ω
1.7
1.1
1.9
1.4 1.3
1.0 1.0
1.6 1.4
ns
tH Hold
time
Data after CLK ↑
Data after LE ↓ CLK high
Data after LE ↓ CLK low
1.7 1.6 1.3
2.0 1.8 1.5
1.6 1.5 1.2
∆t/∆v(2) Input Transition Rise or Fall
0 10 0 10 0
Notes:
1. See test circuit and waveforms.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
10 ns/V
Switching Characteristics Over Operating Range(1)
Parameters
From
(Input)
To
(Output)
Conditions(1)
VCC = 2.5V ± 0.2V
Min.(2) Max.
VCC = 2.7V VCC = 3.3V ± 0.V
Min.(2) Max. Min.(2) Max. Units
fMAX
150 150 150 MHz
A or B B or A
5.1 4.7 1 3.9
tPD LE A or B
5.9 5.5 1.3 4.7
CLK A or B CL = 50pF
6.6
tEN OEAB B RL = 500W 1.0 5.7
6.6 1.1 5.5
5.4 1.0 4.6 ns
tDIS OEAB B
6.1 5.7 1.5 5.0
tEN OEBA A
6.2 6.2 1.0 5.2
tDIS OEBA A
5.4
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4.6 1.0 4.3
Operating Characteristics, TA = 25ºC
Parameter
CPD Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
Test Conditions
CL = 50pF
f = 10 MHz
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Typical
40 51
66
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS8155A 11/06/00
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH16500.PDF ] | |
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