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PDF AT-32032 Data sheet ( Hoja de datos )
| Número de pieza | AT-32032 | |
| Descripción | High Performance NPN Silicon Bipolar Transistor | |
| Fabricantes | AVAGO | |
| Logotipo |  |
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AT-32032
Low Current, High Performance
NPN Silicon Bipolar Transistor
Data Sheet
Description
Avago’s AT-32032 is a high performance NPN bipolar
transistor that has been optimized for maximum ft at
low voltage operation, making it ideal for use in battery
powered applications in cellular/PCS and other wireless
markets. The AT-32032 uses the miniature 3 lead SOT-323
(SC-70) plastic package.
Optimized performance at 2.7 V makes this device ideal
for use in 900 MHz, 1.8 GHz, and 2.4 GHz systems. Typical
amplifier design at 900 MHz yields 1 dB noise figures with
15 dB associated gain at 2.7 V and 5 mA bias condition,
with noise performance being relatively insensitive to
input match. High gain capability at 1 V and 1 mA makes
this device a good fit for 900 MHz pager applications.
Moreover, voltage breakdown is high enough for use
at 5 V.
The AT-32032 belongs to Avago’s AT-3XXXX series bipolar
transistors. It exhibits excellent device uniformity, per-
formance and reliability as a result of ion-implantation,
self-alignment techniques, and gold metalization in the
fabrication process.
Features
• High Performance Bipolar Transistor Optimized for Low
Current, Low Voltage Applications at 900 MHz, 1.8 GHz,
and 2.4 GHz
• Performance at 2.7 V, 5 mA:
900 MHz: 1 dB NF, 15 dB GA
1800 MHz: 1.3 dB NF, 11 dB GA
2400 MHz: 1.4 dB NF, 7.5 dB G
• Characterized for End-Of-Life Battery Use (2.7 V)
• Miniature 3-lead SOT-323 (SC-70) Plastic Package
• Lead-free
Applications
• LNA, Oscillator, Driver Amplifier, Buffer Amplifier, and
Down Converter for Cellular and PCS Handsets and
Cordless Telephones
• LNA, Oscillator, Mixer, and Gain Amplifier for Pagers
• Power Amplifier and Oscillator for RF-ID Tag
• LNA and Gain Amplifier for GPS
• LNA for CATV Set-Top Box
3-Lead SC-70 (SOT-323)
Surface Mount Plastic Package
Pin Configuration
COLLECTOR
32
BASE EMITTER
1 page  
AT-32032 Typical Scattering Parameters, Common Emitter, ZO = 50 Ω, VCE = 2.7 V, IC = 2 mA
Freq. S11
GHz Mag Ang dB
S21
Mag Ang dB
S12
Mag Ang
0.5
0.744
-57
14.37
5.232
130
-23.72
0.065
60
0.75
0.609
-78
12.86
4.394
112
-21.73
0.082
52
1.0
0.489
-96
11.40
3.714
98
-20.58
0.094
49
1.5
0.351
-129
8.86
2.774
77
-19.05
0.112
48
2.0
0.280
-158
6.93
2.221
61
-17.56
0.133
49
3.0
0.236
149
4.28
1.636
34
-14.08
0.198
50
4.0
0.258
105
2.58
1.346
11
-10.62
0.295
44
5.0
0.317
72
1.36
1.170
-8
-7.54
0.420
30
6.0
0.387
51
0.43
1.051
-26
-5.11
0.555
13
7.0
0.455
34
-0.24
0.973
-42
-3.28
0.686
-8
8.0
0.516
19
-0.80
0.913
-58
-2.24
0.772
-30
9.0
0.563
3
-1.39
0.852
-74
-1.86
0.807
-52
10.0
0.610
-14
-2.00
0.794
-89
-2.00
0.795
-73
S22
Mag
0.839
0.755
0.694
0.625
0.592
0.561
0.541
0.510
0.447
0.373
0.367
0.431
0.504
Ang
-22
-28
-31
-37
-43
-59
-78
-103
-135
-178
129
86
55
AT-32032 Typical Noise Parameters,
Common Emitter, ZO = 50 Ω, VCE = 2.7 V, IC = 2 mA
Freq. Fmin
Γopt
GHz dB
Mag Ang
0.9 0.9 0.38 57
1.8 1.2 0.41 124
2.0 1.2 0.42 136
2.5 1.4 0.44 176
3.0 1.6 0.47 -152
3.5 1.8 0.52 -123
4.0 2.1 0.57 -100
Rn
ohms
10.6
6.2
5.3
3.4
4.9
10.5
20.6
gmax = maximum available gain (MAG) if k > 1
gmax = maximum stable gain (MSG) if k < 1
k = stability factor
M AG
=
S21
S12
(k ± √k2–1)
MSG = |S21| /|S12|
k
=
1
– |S11| 2 – |S22|2
2*|S12| |S21|
+
|D|2
;
D
=
S11S22
–
S12
S21
Gassoc
dB
14.0
10.5
9.4
8.4
7.5
6.9
6.2
20 1.25
16 1
12 0.75
8 0.5
4 gmax
dB(S[2,1])
0k
01 2 3 4
FREQUENCY (GHz)
5
0.25
0
6
Figure 10. Gain vs. Frequency at 2.7 V, 2 mA.
Note: dB(|S 21|) = 20 * log(|S21|)
5 Page 
AT-32032 Application Information
The AT-32032 is described in a low noise amplifier for use
in the 800 to 900 MHz frequency range. The amplifier is
designed for use with .032 inch thickness FR-4 printed
circuit board material.
900 MHz LNA Design
The amplifier is designed for a Vce of 2.7 volts and Ic of 5
mA. and a nominal power supply voltage of 3 volts. The
amplifier schematic is shown in Figure 16.
A component list is shown in Figure 17. The artwork
including component placement is shown in Figure 18.
AT-3XX32
AT-4XX32
IN
02/98 AJW
.031 FR-4
OUT
C2
INPUT
L1 Q1
Zo C1 L2
R6 L4
L3
R5
C3 OUTPUT
Zo
R1
C4 R2 R4
C5 VCC = 3 V
R3
Figure 16. Schematic Diagram.
C1,C3
C2
C4,C5
L1
L2
L3
L4
Q1 Silicon
R1
R2
R3
R4
R5
R6
Zo
10 pF chip capacitor
Open circuited stub .275 inch long
1000 pF chip capacitor
8 nH chip inductor (Coilcraft 1008CS-080)
Optional (see R1)
56 nH chip inductor (Coilcraft 1008CS-560)
15 nH chip inductor (Coilcraft 1008CS-150)
Agilent AT-32032 Bipolar Transistor
10 K Ω chip resistor (may want to substitute
a 180 nH chip inductor and 50 W resistor for
lower noise figure, better low freq stability,
the readjust R2)
26.1 K Ω chip resistor (adjust for rated Ic)
3.32 K Ω chip resistor
3.32 K Ω chip resistor
51.1 Ω chip resistor
13 Ω chip resistor (see text)
50 Ω microstripline
Figure 17. Component Parts List.
Vcc
Figure 18. 1X Artwork showing Component Placement.
The input matching network uses a shunt C series L input
impedance matching circuit for low noise. The shunt
C is accomplished with an open circuited stub while a
chip inductor is used for the series element. The output
impedance matching network consists of a series chip
inductor. Bias insertion is accomplished by the use of small
inductors suitably bypassed. A resistor is placed in series
with the output bias decoupling inductor to de-Q the
network and improve in-band and low frequency stability.
Surface mount Coilcraft inductors were chosen for their
small size. Resistor R6 enhances broad band stability
especially in the 9 to 10 GHz frequency range.
Biasing
The bias network is designed for a nominal power supply
voltage of 3 volts. Resistors R1 and R2 are used to adjust
collector current. Resistor R4 can be attached to the
junction of R5 and C5 to improve bias point stability.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AT-32032.PDF ] | |
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