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PDF MT8966 Data sheet ( Hoja de datos )
| Número de pieza | MT8966 | |
| Descripción | Integrated PCM Filter Codec | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
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® ISO2-CMOS MT8960/61/62/63/64/65/66/67
Integrated PCM Filter Codec
Features
• ST-BUS™ compatible
• Transmit/Receive filters & PCM Codec in one
I.C
• Meets AT&T D3/D4 and CCITT G711 and G712
• µ-Law: MT8960/62/64/67
• A-Law: MT8961/63/65/67
• Low power consumption:
Op.: 30 mW typ.
Stby.: 2.5 mW typ.
• Digital Coding Options:
MT8964/65/66/67 CCITT Code
MT8960/61/62/63 Alternative Code
• Digitally controlled gain adjust of both filters
• Analog and digital loopback
• Filters and codec independently user
accessible for testing
• Powerdown mode available
• 2.048 MHz master clock input
• Up to six uncommitted control outputs
• ±5V ±5% power supply
ISSUE 10
May 1995
Ordering Information
MT8964/65AC
18 Pin Ceramic DIP
MT8960/61/64/65AE
MT8962/63AE
MT8962/63/66/67AS
18 Pin Plastic DIP
20 Pin Plastic DIP
20 Pin SOIC
0°C to+70°C
Description
Manufactured in ISO2-CMOS, these integrated filter/
codecs are designed to meet the demanding
performance needs of the digital telecommunications
industry, e.g., PABX, Central Office, Digital
telephones.
ANUL
VX
SD0
SD1
SD2
SD3
SD4
SD5
VR
Transmit
Filter
Analog to
Digital PCM
Encoder
Output
Register
Output
Register
A Register
8-Bits
B-Register
8-Bits
Control
Logic
Receive
Filter
PCM Digital
to Analog
Decoder
Input
Register
VRef GNDA GNDD VDD VEE
Figure 1 - Functional Block Diagram
DSTo
CSTi
CA
F1i
C2i
DSTi
6-19
1 page  
ISO2-CMOS MT8960/61/62/63/64/65/66/67
VRef
An external voltage must be supplied to the VRef pin
which provides the reference voltage for the digital
encoding and decoding of the analog signal. For
VRef = 2.5V, the digital encode decision value for
overload (maximum analog signal detect level) is
equal to an analog input VIN = 2.415V (µ-Law
version) or 2.5V (A-Law version) and is equivalent to
a signal level of 3.17 dBm0 or 3.14 dBm0
respectively, at the codec.
The analog output voltage from the decoder at VR is
defined as:
µ-Law:
VX
[( ) ( )( )]Ref
-0.5 2C
128 + 128
16.5 + S
33
±V
OFFSET
A-Law:
[( )( )]V X
Ref
2C+1
128
0.5 + S
32
±VOFFSETC=0
[( )( )]V X
Ref
2C 16.5 + S
128 32
±VOFFSETC≠0
where C = chord number (0-7)
S = step number (0-15)
VRef is a high impedance input with a varying
capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960
series of codecs is 2.5V ±0.5%. The output voltage
from the reference source should have a maximum
temperature coefficient of 100 ppm/C°. This voltage
should have a total regulation tolerance of ±0.5%
both for changes in the input voltage and output
loading of the voltage reference source. A voltage
reference circuit capable of meeting these
specifications is shown in Figure 5. Analog Devices
’AD1403A voltage reference circuit is capable of
driving a large number of codecs due to the high
input impedance of the VRef input. Normal
precautions should be taken in PCB layout design to
minimize noise coupling to this pin. A 0.1 µF
capacitor connected from VRef to ground and located
as close as possible to the codec is recommended to
minimize noise entering through VRef. This capacitor
should have good high frequency characteristics.
Timing
The codec operates in a synchronous manner (see
Figure 9a). The codec is activated on the first
positive edge of C2i after F1i has gone low. The
digital output at DSTo (which is a three-state output
driver) will then change from a high impedance state
to the sign bit of the encoded PCM word to be
output. This will remain valid until the next positive
edge, when the next most significant bit will be
output.
On the first negative clock edge (after F1i signal has
been internally synchronized and CA is at GNDD or
VEE) the logic signal present at DSTi will be clocked
into the input shift register as the sign bit of the
incoming PCM word.
The eight-bit word is thus input at DSTi on negative
edges of C2i and output at DSTo on positive edges
of C2i.
F1i must return to a high level after the eighth
clock pulse causing DSTo to enter high impedance
and preventing further input data to DSTi. F1i will
continue to be sampled on every positive edge of
C2i. (Note: F1i may subsequently be taken low
during the same sampling frame to enable entry of
serial data into CSTi. This occurs usually mid-frame,
in conjunction with CA=VDD, in order to enter an 8-bit
control word into Register B. In this case, PCM input
and output are inhibited by CA at VDD.)
NC NC NC NC
876
AD1403A
123
5
4
VRef
0.1 µF
MT8960-67
FILTER/CODEC
NC
+5V
2.5V
Figure 5 - Typical Voltage Reference Circuit
6-23
5 Page 
ISO2-CMOS MT8960/61/62/63/64/65/66/67
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max Units
1 DC Supply Voltages
VDD-GNDD
-0.3
+6.0
VEE-GNDD
-6.0
+0.3
2 Reference Voltage
VRef
GNDA
VDD
3 Analog Input
VX
VEE
VDD
4 Digital Inputs
Except CA GNDD-0.3 VDD+0.3
CA
VEE-0.3
VDD+0.3
5 Output Voltage
SD0-2
GNDD-0.3 VDD+0.3
SD3
VEE-0.3
VDD+0.3
SD4-5
VEE-0.3
VDD+0.3
6 Current On Any Pin
II 20
7 Storage Temperature
TS -55 +125
8 Power Dissipation at 25°C (Derate 16 mW/°C above 75°C)
PDiss
500
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to GNDD unless otherwise stated
V
V
V
V
V
V
V
V
V
mA
°C
mW
Characteristics
Sym Min Typ* Max Units
Comments
1 Supply Voltage
2 Voltage On Digital Ground
VDD 4.75 5.0 5.25
V
VEE -5.25 -5.0 -4.75
V
VRef
2.5
V See Note 1
VGNDD -0.1 0.0 +0.1 Vdc Ref. to GNDA
-0.4 0.0 +0.4 Vac Ref. to GNDA 400ns max.
duration in 125µs cycle
3 Operating Temperature
TO 0
+70 °C
4 Operating Current VDD
VEE
IDD
IEE
3.0 4.0 mA All digital inputs at VDD
3.0 4.0 mA or GNDD (or VEE for CA)
VRef
IRef
2.0
µA Mean current
5
Note 1:
Standby Current
VDD
VEE
IDDO
IEEO
0.25
0.25
Temperature coefficient of VRef should be better than 100 ppm/°C.
1.0
1.0
mA All digital inputs at VDD
mA or GNDD (or VEE for CA)
DC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless
otherwise specified.
Characteristics
Sym Min Typ* Max Units
Test Conditions
1 Input Current
Except CA
II
10.0
µA VIN = GNDD to VDD
2
D
I
Input Low
CA IIC
Except CA VIL 0.0
G Voltage
CA
3
I
T
Input High Voltage All Inputs
VILC
VIH
VEE
2.4
4 A Input Intermediate CA
L Voltage
VIIC 0.0
10.0
0.8
µA VIN = VEE to VDD
V
VEE+1.2
V
5.0 V
0.8 V
5 Output Leakage DSTo
Current (Tristate) SD3-5
I0Z
±0.1
10.0
µA Output High Impedance
µA
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
6-29
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MT8966.PDF ] | |
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