MT8964 Datasheet PDF ( Pinout ) - Integrated PCM Filter Codec

MT8964 Datasheet PDF - Zarlink Semiconductor

Part Number	*MT8964*
Description	Integrated PCM Filter Codec
Manufacturers	Zarlink Semiconductor
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ISO2-CMOS MT8960/61/62/63/64/65/66/67

Integrated PCM Filter Codec

Data Sheet

Features

• ST-BUS compatible

• Transmit/Receive filters & PCM Codec in one I.C

• Meets AT&T D3/D4 and CCITT G711 and G712

• µ-Law: MT8960/62/64/67

• A-Law: MT8961/63/65/67

• Low power consumption:

Op.: 30 mW typ.

Stby.: 2.5 mW typ.

• Digital Coding Options:

MT8964/65/66/67 CCITT Code

MT8960/61/62/63 Alternative Code

• Digitally controlled gain adjust of both filters

• Analog and digital loopback

• Filters and codec independently user accessible

for testing

• Powerdown mode available

• 2.048 MHz master clock input

• Up to six uncommitted control outputs

• ±5 V ±5% power supply

February 2005

Ordering Information

MT8960/61/64/65AE

MT8962/63AE

MT8962/63/66/67AS

MT8963ASR

MT8960AE1

MT8962/63AE1

MT8962AS1

MT8963AS1

18 Pin PDIP

20 Pin PDIP

20 Pin SOIC

18 Pin PDIP*

20 Pin PDIP*

20 Pin SOIC*

*Pb Free Matte Tin

-40°C to +85°C

Tubes

Tape & Reel

Tubes

Description

Manufactured in ISO2-CMOS, these integrated

filter/codecs are designed to meet the demanding

performance needs of the digital telecommunications

industry, e.g., PABX, Central Office, Digital telephones.

ANUL

SD0

SD1

SD2

SD3

SD4

SD5

Transmit

Filter

Output

Analog to

Digital PCM

Encoder

Output

A Register

8-Bits

B-Register

8-Bits

Control

Logic

DSTo

CSTi

F1i

C2i

Receive

Filter

PCM Digital

to Analog

Decoder

Input

DSTi

VRef GNDA GNDD VDD VEE

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT8960/61/62/63/64/65/66/67

Data Sheet

injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between

0.1 and 1 µF) must be externally connected from this point (ANUL) to the Analog Ground (GNDA).

The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by

means of three binary controlled gain pads.

The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended

specifications. Typical attenuations are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above.

The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor array, or alternatively,

into an external capacitive load of 250 pF when the chip is in the test mode. The digital encoder generates an eight-

bit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB)

and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value.

Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign

plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3

specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the

CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code

corresponding to the analog voltage, VIN, at VX input.

The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bits of

the 125 µs sampling frame.

Receive Path

An eight-bit PCM encoded digital word is received on DSTi input once during the 125 µs period and is loaded into

the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz

sample and hold circuit integrates this charge and holds it for the rest of the sampling period.

The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter

consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and

smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to

compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The

absolute gain of the receive filter can be adjusted from 0 dB to -7 dB in 1 dB steps by means of three binary

controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and

AT & T recommended specifications.

Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V

peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits.

VRef

An external voltage must be supplied to the VRef pin which provides the reference voltage for the digital encoding

and decoding of the analog signal. For VRef = 2.5 V, the digital encode decision value for overload (maximum

analog signal detect level) is equal to an analog input VIN = 2.415 V (µ-Law version) or 2.5 V (A-Law version) and is

equivalent to a signal level of 3.17 dBm0 or 3.14 dBm0 respectively, at the codec.

The analog output voltage from the decoder at VR is defined as:

µ-Law:

[( ) ( )( )]Ref

-0.5

128

16.5 + S

±VOFFSET

A-Law:

[( )( )]V X

Ref

2C+1

128

0.5 + S

±VOFFSETC=0

Zarlink Semiconductor Inc.

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MT8964 Datasheet PDF - Zarlink Semiconductor

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