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PDF MSM32R Data sheet ( Hoja de datos )
| Número de pieza | MSM32R | |
| Descripción | Sea Of Gates and Customer Structured Arrays | |
| Fabricantes | OKI | |
| Logotipo |  |
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DATA SHEET
OKI
ASIC
PRODUCTS
MSM30R/32R/92R
0.5µm Sea Of Gates and
Customer Structured Arrays
August 2002
1 page  
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– I MSM30R/32R/92R I
ARRAY ARCHITECTURE
The primary components of a 0.5µm MSM30R/32R/92R circuit include:
• I/O base cells
• Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)
• VDD and VSS pads dedicated to wafer probing
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC)
and output drive transistors (VDDO and VSSO).
Configurable I/O pads
for VDD, VSS, or I/O
I/O base cells
Separate power bus (VDDC, VSSC) for
internal core logic (2nd metal/3rd metal
1,2, or 3 layer metal
interconnection in
core area
Core base cell
with 4 transistors
VDD, VSS pads (4) in each
corner for
wafer probing only
Separate power bus (VDDO, VSSO)
over I/O cell for output buffers(2nd
metal/3rd metal)
Figure 7. MSM30R0000 Array Architecture
MSM92R000 CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify the macrocell functions required and the minimum array size to hold the macrocell
functions.
Oki Semiconductor
3
5 Page 
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– I MSM30R/32R/92R I
.
AC Characteristics (VDD = 3.3 V, VSS = 0 V, Tj = 25° C)
Parameter
Driving Type
Internal gate
propagation delay
Inverter
1X
2X
4X
1X
2-input NAND
2X
4X
1X
Inverter
2X
4X
1X
2-input NAND
2X
4X
Toggle frequency
Input buffer
propagation delay
TTL level,
normal input buffer
Conditions [1] [2]
F/O= 2 , L= 0 mm
F/O= 2,
standard wire
length
F/O= 1,
L= 0 mm
F/O= 2 ,
Rated Value [3]
0.12
0.10
0.08
0.17
0.14
0.12
0.28
0.20
0.13
0.36
0.24
0.17
630
0.41 (typ)
Unit
ns
MHz
Output buffer
propagation delay
Output buffer
transition times [4]
TTL level, 5V tolerant
input buffer
Push-pull,
Normal output buffer
3-state, 5V tolerant
output buffer
Push-pull,
Normal output buffer
3-state, 5V tolerant
output buffer
4 mA
8 mA
12 mA
4 mA
12 mA
4 mA
standard wire
length
CL= 20 pF
CL= 50 pF
CL= 100 pF
CL= 20 pF
CL= 75 pF
CL= 20 pF
0.61 (typ)
1.87 (typ)
2.14 (typ)
2.71 (typ)
2.29 (typ)
4.09 (r) (typ)
3.85 (f) (typ)
3.18 (r) (typ)
4.00 (f) (typ)
1. Input transition time in 0.2ns / 3.3V
2. Typical condition in VDD=3.3V and Tj=25°C.
3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.
4. Output rising and falling times are both specified over a 10%-90% range.
ns
Oki Semiconductor
9
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MSM32R.PDF ] | |
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