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PDF N141C6-L01 Data sheet ( Hoja de datos )
| Número de pieza | N141C6-L01 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CMI MEI | |
| Logotipo |  |
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Doc No.:
Issued Date: Jan. 24, 2008
Model No.: N141C6 - L01
Tentative
TFT LCD Tentative Specification
MODEL NO.: N141C6 - L01
Customer:
Approved by:
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Doc No.:
Issued Date: Jan. 24, 2008
Model No.: N141C6 - L01
Tentative
2 ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature
Operating Ambient Temperature
Shock (Non-Operating)
Vibration (Non-Operating)
TST
TOP
SNOP
VNOP
Note (1) (a) 90 %RH Max. (Ta Љ 40 ºC).
Value
Min. Max.
-20 +60
0 +50
- 220/2
- 1.5
Unit
ºC
ºC
G/ms
G
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel display surface area should be 0 ºC Min. and 60 ºC Max..
Relative Humidity (%RH)
Note
(1)
(1), (2)
(3), (5)
(4), (5)
100
90
80
60
Operating Range
40
20
10 Storage Range
-40 -20
0 20 40 60 80
Temperature (ºC)
Note (3) 1 time for ± X, ± Y, ± Z. for Condition (220G / 2ms) is half Sine Wave,.
Note (4) 10 ~ 500 Hz, 30 min / Cycle, 1 cycles for each X, Y, Z axis.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid
enough so that the module would not be twisted or bent by the fixture.
The fixing condition is shown as below:
At Room Temperature
LCD Module
Side Mount Fixing Screw
Gap=2mm
Bracket
Side Mount Fixing Screw
Stage
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Doc No.:
Issued Date: Jan. 24, 2008
Model No.: N141C6 - L01
Tentative
5 INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol
1 Test Loop
2 VEDID
3 VSS
4 CLKEDID
5 DATAEDID
6 VSS
7 Odd_Rin0-
8 Odd_Rin0+
9 VSS
10 Odd_Rin1-
11 Odd_Rin1+
12 VSS
13 Odd_Rin2-
14 Odd_Rin2+
15 VSS
16 Odd_ClkIN-
17 Odd_ClkIN+
18 VSS
19 Even_Rin0-
20 Even_Rin0+
21 VSS
22 Even_Rin1-
23 Even_Rin1+
24 VSS
25 Even_Rin2-
26 Even_Rin2+
27 VSS
28 Even_ClkIN-
29 Even_ClkIN+
30 Test Loop
31 CONNTST
32 Vcc
33 Vcc
34 BIST
35 NC
36 VSS
37 VSS
38 PWM_BL
39 VBL-
40 VBL-
41 VBL-
42 VBL-
43 NC
44 VBL+
45 VBL+
46 VBL+
47 VBL+
48 SMB_DATA
49 SMB_CLK
50 CONNTST
Description
Test Loop (only to pin 30)
EDID 3.3V power
Ground
EDID clock
EDID data
Ground
- LVDS differential data input (R0-R5, G0)
+ LVDS differential data input (R0-R5, G0)
Ground
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
Ground
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
Ground
- LVDS differential clock input (odd pixels)
+ LVDS differential clock input (odd pixels)
Ground
- LVDS differential data input (R0-R5, G0) (even pixels)
+ LVDS differential data input (R0-R5, G0) (even pixels)
Ground
- LVDS differential data input (G1-G5, B0-B1) (even pixels)
+ LVDS differential data input (G1-G5, B0-B1) (even pixels)
Ground
- LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
+ LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
Ground
- LVDS differential clock input (even pixels)
+ LVDS differential clock input (even pixels)
Test Loop (only to pin 1)
Connector test (this pin connected to pin 50 only) See note 1
Power Supply +3.3 V (typical)
Power Supply +3.3 V (typical)
Panel Self Test
no connect
Ground
Ground
PWM brightness control
Ground
Ground
Ground
Ground
no connect
7V - 20V LED power
7V - 20V LED power
7V - 20V LED power
7V - 20V LED power
SMBus data
SMBus clock
Connector test (this pin to be connected to pin 31 only) See note 1
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