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PDF ML610Q409 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q409 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML610Q409 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ML610Q407/ML610Q408/ML61Q0409
8-bit Microcontroller with a Built-in LCD driver
FEDL610Q409-05
Issue Date: May.23, 2014
GENERAL DESCRIPTION
ML610Q407/ML610Q408/ML610Q409 is a high-performance 8-bit CMOS microcontroller into which peripheral circuits, such
as synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around
LAPIS Semiconductor-original 8-bit CPU nX-U8/100. ML610Q407/ML610Q408/ML610Q409 operates in both high/low-speed
mode and power-saving mode, it is most suitable for battery operated products.
The short TAT are entertained by offering MTP version ML610Q407(P)/ML610Q408(P)/ML610Q409(P).
ML610Q407P/ ML610Q408P/ML610Q409P support industrial temperature -40°C to +85°C, are added to the product lineup.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function (MTP version only)
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
2µs (@500kHz system clock)
0.5µs(@2MHz system clock)
• Internal memory
− Internal 16KByte Flash ROM (8K×16 bits) (including unusable １K Byte TEST area)
− Internal 1KByte Data RAM (1024×8 bits)
• Interrupt controller
− 1 non-maskable interrupt sources
Internal source: 1 (Watch dog timer)
− 27 maskable interrupt sources
Internal sources: 14 (SSIO0, SSIO1, Timer0, Timer1, Timer2, Timer3, UART０, Melody0, RC-A/D converter, PWM0,
TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz)
External sources: 13 (P00, P01, P02, P03, P04, P50, P51, P52, P53, P54, P55, P56, P57)
(One interrupt request is generated from P50 to P57 interrupt sources.)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
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1 page  
FEDL610Q409-05
ML610Q407/ML610Q408/ML610Q409
BLOCK DIAGRAM
ML610Q407/ML610Q408/ML610Q409 Block Diagram
Figure 1 show the block diagram of the ML610Q407/ML610Q408/ML610Q409.
“*” indicates the secondary function of each port.
“(*1)”： 29seg×5com, 30seg×4com, 31seg×3com, and 32seg×2com selectable
“(*2)”： 33seg×5com, 34seg×4com, 35seg×3com, and 36seg×2com selectable
“(*3)”： 37seg×5com, 38seg×4com, 39seg×3com, and 40seg×2com selectable
VDD
VSS
RESET_N
TEST0
TEST1_N
XT0
XT1
LSCLK*
OUTCLK*
VDDL
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100)
GREG
0～15
ELR1～3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
RESET &
TEST
OSC
Power
INT
1
RC-ADC
×2
RAM
1Kbyte
Interrupt
Controller
INT
1 WDT
INT
4 TBC
Capture
×2
INT
4 8bit Timer
×4
ECSR1～3
DSR/CSR
PC
BUS
Controller
INT
2
INT
1
INT
1
INT
1
INT
6
Program
Memory
(MTP)
16Kbyte
SSIO
×2
UART
PWM
Melody
GPIO
Display
Allocation
RAM
Display
register
320bit
LCD
Driver
LCD
BIAS
VPP
SCK0*
SIN0*
SOUT0*
SCK1*
SIN1*
SOUT1*
RXD0*
TXD0*
PWM0*
MD0*
P00 to P04
P20 to P22, P24
P30 to P35
P40 to P47
P50 to P57
P60 to P67 (ML610Q407)
P60 to P63 (ML610Q408)
COM0 to COM4 (*1)(*2)(*3)
SEG0 to SEG31 (ML610Q407) (*1)
SEG0 to SEG35 (ML610Q408) (*2)
SEG0 to SEG39 (ML610Q409) (*3)
VL1, VL2, VL3
C1, C2
Figure 1 ML610Q407/ML610Q408/ML610Q409 Block Diagram
5/34
5 Page 
ML610Q409 Chip Pin Layout & Dimension
FEDL610Q409-05
ML610Q407/ML610Q408/ML610Q409
VSS 67
P20 68
P21 69
P22 70
P24 71
P00 72
P01 73
P02 74
P03 75
P04 76
P30 77
P31 78
P34 79
P32 80
P33 81
P35 82
P57 83
P56 84
P55 85
P54 86
P53 87
VPP 88
2.27mm
44 SEG17
43 SEG16
42 SEG15
41 SEG14
40 SEG13
39 SEG12
38 SEG11
37 SEG10
36 SEG9
35 SEG8
34 SEG7
33 SEG6
2.23mm
32 SEG5
31 SEG4
30 SEG3
29 COM4/SEG2
28 COM3/SEG1
27 COM2/SEG0
26 COM1
25 COM0
24 C2
23 C1
Y
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.27 mm × 2.23 mm
PAD count: 88 pins
Minimum PAD pitch: 80 µm
PAD aperture: 70 µm×70 µm
Chip thickness: 350 µm
Voltage of the rear side of chip: VSS level.
Figure 7 ML610Q409 Chip Layout & Dimension
11/34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML610Q409.PDF ] | |
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